Tutorial: Verilog Simulation with Cadence using Signalscan

Tutorial: Verilog Simulation with Cadence PSD 14.0 using SignalScan

Writing a Testbench:

To simulate a design one may write a testbench in verilog where input signal timings can be provided. Cadence comes with very handy tools for writing and simulating testbenches. The simplest way to write it requies the following steps:

1. Generating Template:

Run projmgr from your prompt, choose Concept HDL Expert, Open your project/design if you havent done so.
Go to Flows->Programmable IC.
Click on Verify Logic. Click Setup.. button. Select Stimulus tab. It will look like the following figure:
Select the radio button Generate Testbench
You may want to specify the timescale according to your requirement. The default is 1ns/100ps. You may not always change it to whatever you like. If you use cadence for your FPGA design which actually generates the verilog module for you incorporates other libraries as well (like glbl, alias_bit..etc). If the timescale specified in the verilog files for those libraries do not match with your testbench timescale you may not get the simulation result as expected. So it is better to use the default value.
However, if you are simulating a verilog module written all by yourself you can specify your own timescale. To know more about timescales please consult any verilog tutorial.
Now click on the button Generate. The testbench template is usually generated as: your_project_dir/worklib/testfixture/your_project_name_sch_1/verilog.v
Click OK when it shows mesage "TestBench Template File generated successfully".

2. Providing Timing information:

Use any text editor (such as emacs) to edit the file testbench.v
For a design named my_design it may look as follows:

       
// generated by Testbench Utility   Thu Apr  5 15:05:35 2001


`timescale 1ns/100ps

module testfixture ;
    wire [5:0] a_gain_select;
    wire \f_oea* ;
    wire \f_oeb* ;
    .
    .
    .
    reg [11:0] reg_lad;
    reg \ads* ;
    reg \cs0* ;
    reg clk;	
    .
    .
    .	    
 
    my_design top (a_gain_select, \f_oea* , \f_oeb* ...... \ads* , \cs0*.....);

endmodule

Now start typing from the bottom of the file just above endmodule. To add a clock that will run continuously add the following lines:
```
	initial
	     begin
		$clkdef(lclk, 0, 5, 10);
	end
       
```
Here the signal 'lclk' is a input signal to the fpga/ or the module you are designing which you want to run as a clock. 0, 5 specifies the time range it will be high and 10 specifies its time period in nanoseconds.
To specify timing of the input signals use '#' sign. Please refer to the following example:
```
	 always
	      begin
		 #0  \ads* = 1'b0; \cs0* = 1'b1;
		 #10 \ads* = 1'b1; 
		 #20 \ads* = 1'b0; \cs0* = 1'b0;
		 #50 \cs0* = 1'b1;
	 end
       
```
The 'always-end' block enables the same simulation to run again and again. One can also use "initial-begin" block in which case it will run only for once. But by several trial and error for the CADENCE installed in CEDCC it was found that we need to run it in continuous mode. If someone can do it without running it continously please let us know.
the syntax 1'b0 specifies that the signal is 1 bit and you set it to zero. Some examples follow:
LA = 4'b0110    -- LA is a 4 bit bus, assigned a BINARY value 0110.
LA = 8'hF9    -- LA is a 8 bit bus, assigned a HEX value F9.
LA = 12'hz    -- LA is a 12 bit bidirectional bus, assigned high impedance

after typing all the testbench verilog.v file should look like following:
```
// generated by Testbench Utility   Thu Apr  5 15:05:35 2001


`timescale 1ns/100ps

module testfixture ;
    wire [5:0] a_gain_select;
    wire \f_oea* ;
    wire \f_oeb* ;
    .
    .
    .
    reg [11:0] reg_lad;
    reg \ads* ;
    reg \cs0* ;
    reg clk;	
    .
    .
    .	    
 
    my_design top (a_gain_select, \f_oea* , \f_oeb* ...... \ads* , \cs0*.....);

    initial
	begin
		$clkdef(lclk, 0, 5, 10);
    end

    always
	begin
	  #0  \ads* = 1'b0; \cs0* = 1'b1;
	  #10 \ads* = 1'b1; 
	  #20 \ads* = 1'b0; \cs0* = 1'b0;
	  #50 \cs0* = 1'b1;
    end

endmodule
```
Now save the file and go to simulation step. For different simulations you can create different testbenches with different names. But only one can be simulated once.

Simulating a TestBench:

After you are done with writing the testbench you are ready for viewing the simulation results. The steps are as follows:

You you havent closed the "Setup Verify-XL" window, now select the radio button "Include Testbench". Otherwise open your project again. Goto Flows->Programmable IC. Click on Verify Logic->Setup-->Stimulus-->Include Testbench.
In the "Details" dialog box click on "Browse" to select your testbench file. This should be the file you just have written.
Click OK.
Click Run. If everything runs fine and verilog can compile the testbench without any error The following window appears:
Now go to Tools->Navigator.. You can also bring the navigator by clicking the Star icon from the top.
Click on the test module name from the left. For our example it is called "testfixture". This will show all the signals associated with that module. Select different signals that you want to view in simulation window. You can use "Cntrl" key to select multiple signals.
After you select the signals click on the waveform view icon to invoke signalscan. You can also go to Tools->Waveform.. from Cadence Verilog-XL gui window.
The signalscan window should pop up showing all your selected signals. Initially all the signals will have values "u", which is undefined, and the signal waveforms will look like straight purple lines.
Now go back to Cadence Verilog-XL gui window. Press Cntrl-R to run the simulation. You can also click on the icon Or can do it going Control->Run.
As soon as you run it stop it again clicking Pause Icon.
Switch to Signal Scan window and you will be able to see the simulation waveforms. Play with it. You can Zoom out/ Zoom in for better view. Also you can select on any bus signal and click on "Expand" button to see the values of each bit.

Finally your simulation waveforms should look something like the following:

For further information please consult the verilog tutorial provided in Openbook that comes with Cadence (starting at page 37). To contact author of this page email sharifs@psu.edu

[ Return to the Penn State Cadence^®University Program Page ]

[ DAI SignalScan User's Guide ] [ Cadence Design Systems ] [ PC based verilog tutorial software ]

This page has been accessed times since April 9, 2001

Last Modified Thursday, October 14, 2004 15:40:32