EE 497I
Fall 1999
Rapid System Prototyping
Quiz #2 – November 9, 1999
ANSWERS – all answer links refer to slides in RASSP Module 60 (VHDL Synthesis)
AVERAGE SCORE = 12.6 (out of 20) STANDARD Deviation = 2.3
1. (2 points) Which
of the following ensures that the implementation of the design matches the
requirements of the customer (i.e., the right system is designed / synthesized).
a.
Design Verification
b.
Design Validation
c.
Design Scheduling
d.
Design Specification
Answer: (b)
Design Validation LINK TO
S00017.HTM
2. (2 points) Which of the following ensures that the implementation
of the design is consistent with the specification (i.e., the system is designed
right).
a.
Design Verification
b.
Design Validation
c.
Design Scheduling
d.
Design Implementation
Answer: (a) Design Verification.
LINK TO S00017.HTM
3. (2 points) Which of the following are merits of RTL synthesis?
a. Capture of a digital design at the register-transfer level in VHDL improves productivity over logic synthesis tools.
b. Mapping to libraries of high-level components (multipliers, adders) is possible, and a large subset of VHDL RTL constructs are supported.
c. RTL offers good control over the synthesis process in terms of the final architecture.
d. All of the above
Answer: (d) All of the above. LINK TO S00041.HTM
4. (2 points) Which of
the following statements is FALSE regarding RTL synthesis?
a.
Until 1997 most vendors supported a different RTL subset of VHDL
b.
Requires specification of the datapath, registers, controller, and
cycle-by-cycle behavior
c.
Resource sharing, resource allocation, scheduling, and mapping tasks are
carried out by the tool itself.
d.
Allows no architectural exploration, and the synthesizer optimizes at the
level of the components and states.
Answer: (c) is FALSE: Resource sharing, resource allocation, scheduling, and mapping tasks have to be carried out by the designer prior to coding at the RTL level, limiting architectural exploration. LINK TO S00041.HTM
5. (2 points) Which of the following types and subtypes are supported by VHDL RTL synthesis?
a. Physical
b. Time
c. Multidimensional array
d. Floating Point
e. none of the above
Answer: (e) none of the above are supported by VHDL RTL synthesis. LINK TO S00061.HTM
6. (2 points)
Which of the following are true statements regarding combinational
circuit synthesis with VHDL RTL Subset.
a.
Concurrent
constructs (e.g. selected signal and conditional signal assignment statements)
can be used for combinational circuits
b.
Sequential
constructs such as PROCESS, IF, CASE, LOOP and WHILE cannot be used for
combinational circuits
c.
Encoders/decoders,
multiplexers/demultiplexers, and ALU’s are all examples of combinational
circuits which can be synthesized using the RTL subset.
d.
Both a and c
e.
All of the above
Answer: (d) Both statements a and c are correct.
Answer b is incorrect since sequential constructs (including process,
case, if, loop and while) CAN be used to create models of combinational
circuits. LINK TO S00119.HTM
7. (2 points) When Flip Flops are inferred using a WAIT statement, asynchronous conditions _________ be modeled in the same process using the WAIT UNTIL construct.
a. can
b. cannot
c. may
d. should
Answer: (b) cannot be modeled. Only a single WAIT statement is allowed per process (it must
be the first statement in the process), and it must be a WAIT UNTIL clock.
Thus, asynchronous conditions cannot be modeled in the same process using
the WAIT UNTIL construct. LINK TO S00130.HTM
8. (3 points) Review the
VHDL model below to determine what type of hardware storage element it
represents.
ENTITY storage_element IS
PORT( d, clk, reset ; IN BIT; q, qbar ;OUT BIT);
END storage_element;
ARCHITECTURE storage_element
OF storage_element IS
signal sig : bit;
BEGIN
PROCESS (
clock, d, reset, sig )
BEGIN
IF reset
= '1' THEN
sig <= '0';
ELSIF clock'EVENT
AND clock = '1' THEN
sig <= d;
END IF;
END PROCESS;
q <= sig;
END
storage_element;
This
VHDL model represents an example of which of the following?
a.
latch with
asynchronous reset
b.
latch with
synchronous reset
c.
flip flop with
synchronous reset
d.
flip flop with
asynchronous reset
e.
none of the above
Answer: (d) flip flop with asynchronous reset. LINK TO S00136.HTM
9. (3 points) Consider the following VHDL code fragment:
clocked
: PROCESS (clk, reset)
BEGIN
IF (reset = '0') THEN
Q <= ’0’;
ELSE
Q <= D;
END IF;
END
PROCESS clocked;
What
does the above clocked:PROCESS synthesize to?
a. A Multiplexor
b. An edge-triggered flip-flop
c. A level sensitive latch
d. None of the above
Answer: (a) A multiplexor is synthesized. The clock edge specification is not included in the model, and there are no conditions where the output Q is left unassigned. LINK TO S00146.HTM
Last Meddled With: 10/14/04
. - D. Landis
