EE 497I   Fall 1999                                                         Rapid System Prototyping

 SOLUTION    Quiz #3 – November 18, 1999     

 AVERAGE SCORE = 12.5 (out of 20)  STANDARD Deviation = 4

 

1. (2 points) The 22V10 Programmable Array Logic (PAL) device discussed in the 11/9 lecture has:

a.       22 logic inputs and 10 outputs

b.      11 logic inputs and 5 outputs

**** c.      11 logic inputs and 10 outputs (11 logic inputs + their complements = 22 signals in the "AND array") ****

d.      22 logic inputs and 5 outputs

 

2. (2 points) The 22V10 and similar PAL devices are considered the ancestors of modern FPGA and CPLD architectures.  Which of the following modern chip families most closely incorporates the early PAL design components?

a.       Xilinx XC4000 Family

*****b.      Altera Max 9000 Family (uses PAL style of macrocell in their LAB)*****

c.      Xilinx XC3000 Family

d.      None of the Above

 

3. (4 points)  One of the Xilinx predefined cells discussed in the 11/16 guest lecture was the startup block.  What is the purpose of the STARTUP block in a Xilinx XC4000 family design?

  The STARTUP primitive is used for Global Set/Reset (of all flip-flops), for global tri-state control, and for user configuration clock (when booting the Xilinx chip from an external PC or other host). 

 

4. (2 points)  What programmable feature is available on the Xilinx IOB (Input/Output Block) which can be used to reduce problems associated with simultaneous output switching?

a.       Passive Pull-Up

*****b.      Slew Rate (programming to reduce slew rate will reduce peak current draw, and minimize the chances of power supply rail collapse)***********

c.      Passive Pull-Down

d.      Boundary Scan

 

5. (4 points)  The Xilinx marketing figure shown below indicates four regions of different signal-processing design  applicability; placed along Complexity Data Rate axes.  Overlaid on the four regions is the applicability range for FPGA- based DSP (between the large dotted lines).  The four alternatives to FPGA solutions are: 1.) Multiple-chip based  DSP, 2.) Single-Chip DSP, 3.)  ASICs, and 4.) Conventional Microprocessor or Microcontroller (MPU/MCU).  On the figure, write the name of the appropriate design style in the appropriate shaded  region.  

 

6. (6 points)  Consider a 512-pin FPGA design which has 300 outputs, uses 5V output logic levels, and operates at a 90MHz clock rate.  Assume that the capacitive loading on each output is 90pf, and that (on the average) there is a transition on each output on every third clock cycle (33% duty cycle).  What is the chip power consumption due solely to the 300 output drivers? 

 

Power  =  P     = C * V2 * f

 

                                    = (90pf * 300) * (5) 2 * (90Mhz * 0.33)

           

                        = 20.25 watts

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Last Meddled With: 10/14/04 . - D. Landis