EE 497I Fall 1998 Rapid System Prototyping
Mid-Semester Exam -- October 22, 1998
In-Class, Open Note (one 8.5" X 11" page) NAME: ____________________________
1.) 15 points. In the space below, list the major steps in a top-down language-based Rapid Prototyping methodology. Assume that the process begins with a specification, and concludes with an FPGA which implements the desired digital system functions. Describe the operations required at each step, the CAD tools used for design and verification at each step, and the design actions necessary for transition to the next step.
n
Executable Specification
n
FPGA Hardware Prototype
2.) 11 points. A high-speed digital system is being designed which will use Application Specific ICs (ASICs). Assume that the total design complexity is 900,000 equivalent 2-input NAND gates, and that Rents rule will apply to the design with constants KP =1.2 and b=0.49
a.) Assume that the design goal is to construct the intended system using six chips of approximately equal complexity. Estimate the number of signal pins required of the packages of each of the six chips.
__________ signal pins per chip
b.) Assume in part b that our design goal has been changed. We now wish to construct the system using chips of approximately equal complexity which are all packaged in a standard package that has 504 signal pins. How many total chips will be required to construct the system?
_____________ chips per system
3.) 16 points. For the system described in problem #2, two different ASIC target technologies are being considered: a Xilinx FPGA and a mask-programmed gate array (MPGA). Assume that the Xilinx FPGA cost is $90 per chip, while the MPGA cost is $45 per chip plus a $20K non-recurring engineering cost.
a.) Calculate the breakeven production volume based solely on cost. This is the production (sales) volume above which the MPGA ASIC is most cost effective, and below which the FPGA is most cost effective.
____________ break even volume
If we use the Xilinx FPGA, we estimate that our product will arrive to market 20 weeks earlier than if we were to use the MPGA ASIC. Assume that the triangular cost model applies, and that the market life of this product is 1.5 years. Determine the lost revenue percentage from developing the MPGA, and then recalculate the break-even volume considering this lost revenue.
_______________________ % lost revenue
_____________ revised break-even volume
4.) (3 points) The VHDL language was originally developed by an Institute of Electrical and Electronic Engineers (IEEE) committee as a standardized language for describing hardware.
a) True
b)
False
5.) (3 points) A VHDL Model which uses abstract constructs (such as If-Then-Else) most likely represents which of the following styles of VHDL model?
a) Behavioral Specification
b) Data Flow Specification
c) Structural Specification
6.) (3 points) Which style of VHDL Model is most appropriate for use during the early stages of a design?
a) Structural model (because components can be easily added and removed)
b) Data Flow (RTL) model (because logic equations can be easily manipulated for design modifications)
c) Behavioral model (because it is implementation independent)
d) Mixture of all three methods (because the appropriate level of abstraction can be chosen which is best suited for our design)
7.) (3 points) Which of the following is the most accurate statement about VHDL entities and architectures?
a) A component can have many entity declarations and many architectures.
b) A component can have many entity declarations but only one architecture.
c) A component can have only one entity declaration and many alternative architectures.
d) A component can have only one entity declaration and only one architecture.
8.) (3 points) Logic gates may have a minimum input pulse width specification (whereby shorter input pulses are not reproduced at the output). If a VHDL model must duplicate this logic behavior, then which of the following delay models should be used?
a) inertial delay model
b) transport delay model
c) delta delay model
d)
any one would produce the desired result
9.) (3 points) Which of the following VHDL Objects provides a convenient mechanism for local storage by limiting scope to the process where they are declared.
a) signals
b) variables
c) constants
d) files
10.) (3 points) VHDL objects of the _______ class are analogous to wires in a design schematic. They have a history of past, present and future values and their assignment is done after a certain delay.
a) signals
b) variables
c) constants
d) files
11.) (4 points) Which of the statements below most accurately identifies any/all errors in the VHDL code fragment?
ENTITY test is
PORT (a, b: IN BIT; y, z: OUT BIT; clock: INOUT BIT);
END test;
ARCHITECTURE example OF test IS
BEGIN
a <= y AND z AND clock;
b <= y NOR z AND clock;
Clock <= NOT clock;
END example;
a) Signals y and z are incorrectly used as inputs within the architecture
b) Signals a and b are incorrectly assigned values within the architecture
c) Both (a) and (b)
d) Code is error free.
12.) (4 points) With reference to the VHDL behavioral model code segment below, which of the following statements is most accurate?
ARCHITECTURE test_behav OF test IS
VARIABLE x : BIT := ‘1’ ;
BEGIN
PROCESS ( in_sig, y)
SIGNAL y : BIT := ‘0’;
BEGIN
X := in_sig XOR y;
Y <= in_sig XOR x ;
END PROCESS;
END test_behav;
a) A variable (x) is incorrectly declared in the process declaration section
b) A signal (y) is incorrectly defined in the architecture declaration section
c) Both the Variable and Signal declarations are incorrect.
d) The code segment is error free
13.) (8 points) List one advantage and one disadvantage of using a Xilinx style FPGA, which employs Static RAM memory technology to store programming information.
List one advantage and one disadvantage of using an Actel style FPGA, which employs one-time programmable "anti-fuse" technology to store programming information.
14.) (11 points.) Shown below is a simple VHDL behavioral model. In the table provided, fill in the logic values for signals a, and b and variable c at times T = 0- (just before the process executes for the first time), at time T = 0+ (after the process executes for the first time, but before any time elapses), and finally at time t=1ns (more than one delta delay after the process has completed execution).
ENTITY timing_example IS END timing_example;
ARCHITECTURE behavioral OF timing_example IS
SIGNAL a, b : BIT := '1';
VARIABLE c : BIT := '0';
BEGIN
PROCESS (a,b)
BEGIN
c := '1';
b <= NOT c;
a <= b NAND c;
END PROCESS;
END behavioral;
TIME LOGIC VALUE
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a |
b |
c |
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T = 0 - |
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T = 0 + |
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T = 1ns |
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15.)
(10 points). Two options are being considered for construction
of a 900K gate digital system. In
option A, six FPGA chips containing 150K gates per chips are used, with each
chip assembled in a package that has 410 signal pins. In option B, four FPGA chips containing 225K gates per chip are
used, with each chip assembled in a package that has 500 signal pins. Estimate the difference in power consumption
resulting from the different number of off-chip driven signals between the two
system options. The following
assumptions are given:
·
One half of all the signal
pins are outputs.
·
25% output duty
cycle (each output changes only once every four clock cycles).
·
The chips are all
clocked at a 200MHz frequency (F).
·
The average
capacitive loading on each output is 40pf
·
The logic signaling
levels on the board are 0-5V.
·
All power
differences arise from dynamic (CVDD2F) output driver
power dissipation