1.) A VHDL Model that exclusively uses concurrent signal assignment statements to describe the functionality of the design most likely represents which of the following styles of VHDL model?

  1. Behavioral Specification
  2. Data Flow Specification
  3. Structural Specification

 

2.) Which of the following delay models should be used to simulate just the effect of logic propagation delays.

  1. inertial delay model
  2. transport delay model
  3. delta delay model
  4. any one of them would serve the purpose

 

3.) Which of the following is not a VHDL data object

  1. signal
  2. variable
  3. wire
  4. constant

 

4.) Which of the following statements are true?

  1. All VHDL processes execute concurrently
  2. Concurrent signal assignment statements are one-line processes
  3. Statements in a process execute sequentially
  4. All of the above

 

5.) The following fragment of code illustrates the use of what VHDL construct?

IF clock’event AND clock = ‘1’ THEN

    output <= input +1

END IF;

  1. attributes
  2. clocks
  3. comments
  4. identifiers

 

6.) Which of the following statements most accurately identifies any errors in the VHDL Code fragment below?

ENTITY test is

PORT (a, b: IN BIT; y, z: OUT BIT; clock: INOUT BIT);

END test;

ARCHITECTURE example OF test IS

BEGIN

a <= y AND z AND clock;

b <= y NOR z AND clock;

Clock <= NOT clock;

END example;
  1. Signals y and z are incorrectly used as inputs within the architecture
  2. Signals a and b are incorrectly assigned values within the architecture
  3. Both (a) and (b)
  4. Code is error free.