Hardware Synthesis Overview Module Module 33
Rapid Prototyping Design Process
Module Goals
Module Outline
Module Outline (Cont.)
Quick and Dirty Definition
The Integrated Circuit Design Process
Why Use Synthesis?
Why Use Synthesis? (Cont.)
Synthesis Goals
Design Constraints
Area vs. Speed
Definitions
Definitions (Cont.)
Gajski and Kuhn’s Y Chart
Levels of Abstraction Architectural Level
Levels of Abstraction Algorithmic Level
Levels of Abstraction Functional Block Level
Levels of Abstraction Logic Level
Levels of Abstraction Circuit Level
The Role of Synthesis
Synthesis Categories
Synthesis Process Overview
Logic Synthesis Tasks (e.g., Mentor Graphics’ AutoLogic)
Logic Reduction/Factorization Berkeley’s Espresso
Logic Reduction/Factorization Berkeley’s Espresso (Cont.)
Logic Reduction Example Berkeley’s Espresso
Logic Reduction Example (Cont.) Berkeley’s Espresso
Register Transfer Level Basic Computer Registers
Register Transfer Level Instruction Fetch Cycle Example
Behavioral Synthesis Tasks
High-level Optimizations
High-level Optimizations (Cont.)
Allocation
Allocation (Cont.)
Square Root Example
High-Level Optimizations Square Root Example
Scheduling Square Root Example
Scheduling (Cont.) Square Root Example
Supported VHDL Constructs (in Mentor Graphics’ Autologic)
Support for Additional VHDL Provisions
Combinatorial Example Process with Intermediate Signal
Combinatorial Example (Cont.) Process with Intermediate Signal
Combinatorial Example Process with Intermediate Variable
Combinatorial Example Selected Signal Assignment
Synthesis of IF-ELSE Statement VHDL Description
Synthesis of IF-ELSE Statement Resulting Schematic
Synthesis of Simple If Statement VHDL Description
Synthesis of Simple If Statement Resulting Schematic
Internal State Example Incorrect Version
Internal State Example Corrected Version
Internal State for Signal Example Unsynthesizable Version
Internal State for Signal Example Synthesizable Version
Internal State for Signal Example Feedback Version
Internal State for Signal Example Synthesizable without Feedback
Internal State for Signal Example No Feedback Version
Clocked Register Definitions Using Sensitivity List
Clocked Register Definitions Using WAIT Statement
Clocked Register Definitions Using BLOCKs
Clocked Register with Logic VHDL Description
Clocked Register with Logic Resulting Schematic
Logic after the Register VHDL Description
Logic after the Register Resulting Schematic
Keys to Success with Synthesis
More Keys VHDL Constructs
Tool Features
Synthesis Entry Points
Common Synthesis Targets
Synthesis Shortcomings
Synthesis and RASSP COMET
Synthesis and RASSP COMET (Cont.)
Hardware Synthesis Flow in COMET
Synthesis in RASSP Modeling and Synthesis Libraries
Summary
References
Email: dll2@psu.edu
Home Page: http://www.cedcc.psu.edu/
Other information: RASSP E&F Program Slides used by PSU -- EE497I Rapid System Prototyping