Register Transfer Level Instruction Fetch Cycle Example

PC Transfer instruction address:
c0t0: MAR <-- PC


Read instruction and increment PC:
c0t1: MBR <-- M, PC <-- PC+1


Transfer OP code and mode bit:
c0t2: OPT <-- MBR(OP), I <-- MBR(I)


Go to indirect cycle:
q'7Ic0t3: R <-- 1


Go to execute cycle:
(q7 + I')c0t3: F <-- 1

[Mano76]

Previous slide

Next slide

Back to first slide

View graphic version

From [Mano76], p. 158.

c0 denotes the fetch cycle.

The four timing signals during this cycle initiate the sequence of micro-operations.

At t3, control makes a decision based on the contents of q7; note that (q7 + I’) is the complement of q7’I.