Supported VHDL Constructs(in Mentor Graphics’ Autologic)

After clause in concurrent signal assignment statement: No (W)
After clause in sequential signal assignment statement: No (W)
Alias declaration: No (E)
Architecture body: Yes
Assertion statement (concurrent): No (W)
Assertion statement (sequential): No (W)
Attribute declaration: Yes
Attribute specification: Yes
Block statement: Yes
Bus signal: Yes
Case statement: Yes
Component declaration: Yes
Component instantiation statement: Yes

Mentor Graphics Corp.

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The table on this and the following three pages comes from [MGC94b], pp .1-13 through 1-15.

Note that some of the unsynthesizable constructs result in warnings (denoted by “(W)”) and some cause the synthesis tool to abort (denoted by “(E)” for Error).