Supported VHDL Constructs (in Mentor Graphics’ Autologic)
Signal assignment, selected (concurrent): Yes
Signal assignment, simple (concurrent): Yes
Signal assignment (sequential): Yes
Signal declaration: Yes
Subprogram declaration: Yes
Subprogram body: Yes
Subtype declaration: Yes
Type conversion: Yes
Type declaration: Yes
Use clause: Yes
Variable assignment statement: Yes
Variable declaration: Yes
Wait statement: Yes