Combinatorial Example Process with Intermediate Signal

ARCHITECTURE rt1 of ao IS
SIGNAL result : BIT;
BEGIN
PROCESS (i0, i1, i2, result)
BEGIN
result <= i0 AND i1;
o0 <= result OR i2;
END PROCESS;
END rt1;

Mentor Graphics Corp.

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From [MGC94b]

Note that result must appear in the process sensitivity list so that the process is retriggered when the signal assignment to it takes place, thus allowing o0 to be assigned the new value of result.