Synthesis of IF-ELSE Statement VHDL Description

ARCHITECTURE rt1 OF if_else_test IS
BEGIN
PROCESS (select0, in0, in1)
BEGIN
IF (select0 = ‘1’) THEN;
out0 <= in0;
ELSE
out0 <= in1;
END IF;
END PROCESS;
END rt1;

Mentor Graphics Corp.

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From [MGC94b]