Synthesis of Simple If StatementVHDL Description

ARCHITECTURE rt1 OF if_test IS
BEGIN
PROCESS (select0, in0)
BEGIN
IF (select0= ‘1’) THEN;
out0 <= in0;
END IF;
END PROCESS;
END rt1;

Mentor Graphics Corp.

Previous slide

Next slide

Back to first slide

View graphic version

From [MGC94b].