Internal State ExampleIncorrect Version

ARCHITECTURE incorrect OF u_internal_e IS
BEGIN
PROCESS (in1)
VARIABLE x : qsim_state;
BEGIN
IF (in1 = ‘1’) THEN
x:= ‘1’;
ELSIF (in1 = ‘0’) THEN
x:= ‘0’;
END IF;
output <= x;
END PROCESS;
END incorrect;

Mentor Graphics Corp.

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From [MGC94b] .

Problem:

ELSIF line makes in “1” appear like a clock in which both edges are used.