Internal State for Signal ExampleUnsynthesizable Version

ARCHITECTURE incorrect OF int_state IS
SIGNAL reslt : qsim_state;
BEGIN
PROCESS (en1, in1, in2)
BEGIN
IF (en1 = ‘1’) THEN
reslt <= in2 AND in1;
END IF;
output <= reslt;
END PROCESS;
END incorrect;

Mentor Graphics Corp.

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From [MGC94b] .

Not synthesizable because “reslt” is assigned conditionally but it is used in assigning the value of output. We need to add “reslt” to the sensitivity list to ensure that its updated value is assigned to output.