Internal State for Signal ExampleSynthesizable Version

ARCHITECTURE correct OF int_state IS
SIGNAL reslt : qsim_state;
BEGIN
PROCESS (en1, in1, in2, reslt)
BEGIN
IF (en1 = ‘1’) THEN
reslt <= in2 AND in1;
END IF;
output <= reslt;
END PROCESS;
END correct;

Mentor Graphics Corp.

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From [MGC94b].

By adding “reslt” to the sensitivity list, we ensure that the process is activated again so that the signal assignment to output can take place with the new value of “reslt”.

This code results in a feedback circuit shown on the next slide