Internal State for Signal ExampleSynthesizable without Feedback

ARCHITECTURE incorrect OF int_state IS
SIGNAL reslt : qsim_state;
BEGIN
PROCESS (en1, in1, in2)
BEGIN
IF (en1 = ‘1’) THEN
reslt <= in2 AND in1;
END IF;
END PROCESS;
output <= reslt;
END correct;

Mentor Graphics Corp.

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From [MGC94b] .

If the feedback is not desired, and the result of the AND needs to be latched, the assignment to output should be done outside the process with a concurrent signal assignment statement.

Note that concurrent signal assignment statements are one line processes with each of the signals on the right hand side appearing in the sensitivity list anyway.