Keys to Success with Synthesis

• Designer must “think in hardware”

  • Be aware of tool-specific “templates”
    • Indicate what will be used; e.g., latch, mux
  • Be aware of relative timing of different signals with respect to the clock edge

• VHDL process is basic unit of RTL description

  • Combinational cloud process
    • Sensitivity lists include all signals in right-hand-side of logic equations
  • Register-instantiation process
    • Only clock and/or reset signals in sensitivity lists
    • Inputs should not feed non-registered outputs, or simulation results will not be accurate (because those inputs will not appear in the sensitivity list)

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Largely from [Warmke95].