Synthesis and RASSPCOMET (Cont.)
- State typed_identifier_list
A list of typed variables used to store the state of the entity. These variables maintain their values from one entity invocation to the next
- Modifies identifier_list
List of variables and signals this entity can modify. All elements listed must be defined in the state clause or in the entity’s port declaration and of type out, inout, or buffer
- VHDL_type based on logical_expression
Associates a user-defined VHDL type with a formal, logical definition. This allows inferences involving user-defined types