References
[Dirkes88] Dirkes, Beth, “Architectural Partitioning in the System Architect’s Workbench”, presented as part of The System’s Architect Workbench tutorial presented at Carnegie Mellon University, May 17-18, 1988.
[Thomas90] Thomas, D.E., Lagnese, E.D., Walker, R.A., Nestor, J.A., Rajan, J.V., and Blackburn, R.L., Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench, Kluwer Academic Publishers, 1990, p. 3.
[Synopsys94], Synopsys, Inc., Making the Transition to High-Level Design, 1994.
[de Geus89] de Geus, Aart J., “Logic Synthesis Speeds ASIC design”, IEEE Spectrum, August, 1989.
[Parker84] Parker, Alice, “Automated Synthesis of Digital Systems”, IEEE Design and Test, November, 1984.
[Smith88] Smith, David, “What is Logic Synthesis”, VLSI Design and Test, October, 1988.
[MGC92] Mentor Graphics Corporation, Introduction to AutoLogic and Design Synthesis, November, 1992.
[Katz94], Katz, Randy H., Contemporary Logic Design, The Benjamin/Cummings Publishing Company, 1994.
[Mano76] Mano, M. Morris, Computer System Architecture, Prentice-Hall, Inc., 1976
[McFarland90] McFarland, Michael C., and Parker, Alice C., Camposano, Raul, “The High-Level Synthesis of Digital Systems”, Proceedings of the IEEE, February, 1990.