Test Technology OverviewModule 43

Table of Contents

Test Technology OverviewModule 43

Rapid Prototyping Design Process

Module Goals

Module Outline

Module Outline (Cont.)

Module Outline (Cont.)

Module Outline

IntroductionThe Testing Problem

The Testing Problem

The Testing Problem (Cont.)

TestingWhich Type is Closest to Optimum?

TestingWhich Type is Closest to Optimum?(Cont.)

TestingCurrent Practice

Testingand Rapid Prototyping

Module Outline

Fault Attributes

Fault Modeling

Fault Models

Single Stuck-at Fault Model

Single Stuck-at Fault Model(Cont.)

Multiple Stuck-at Fault Model

Stuck-open Fault Model

Stuck-open Fault Model(Cont.)

Bridging Fault Model

Bridging Fault Model(Cont.)

Delay Fault Model

Transitional Delay Fault Model

Transitional Fault Model

Path Delay Fault Model

Module Outline

Test GenerationDefinitions

Test Generation Definitions (Cont.)

Test Generation Definitions (Cont.)

Test Generation Definitions (Cont.)

Test Generation Process

Test Generation/Testing Disconnect

Test Generation/Testing Disconnect (Cont.)

Module Outline

Automatic Test Pattern Generation (ATPG) Algorithms

Pseudorandom Test Generation

PseudorandomTest Generation (Cont.)

Ad-Hoc

D Algorithm

D Algorithm (Cont.)

D Algorithm (Cont.)

PODEM

PODEM (Cont.)

FAN and Related Algorithms

Others...

Sequential Circuit Test Generation

Sequential Circuit Test Generation (Cont.)

Module Outline

Fault SimulationDefinitions

Fault SimulationDefinitions (Cont.)

Fault Tables

Fault Table Reduction

Fault Simulation Algorithms

Fault Simulation Algorithms(Cont.)

Parallel Fault Simulation

Parallel Fault Simulation(Cont.)

Parallel Fault Simulation(Cont.)

Deductive Fault Simulation

Deductive Fault Simulation(Cont.)

Concurrent Fault Simulation

Concurrent Fault Simulation(Cont.)

Parallel Pattern Single Fault Propagation

Sequential Circuit Fault Simulation

Sequential Circuit Fault Simulation (Cont.)

Module Outline

Introduction

Module Outline

IDDQ Testing

IDDQ Testing (Cont.)

IDDQ Testing (Cont.)

IDDQ Testing (Cont.)

IDDQ Fault Modeling

IDDQ Fault Modeling(Cont.)

IDDQ Test Generation

IDDQ Measurement Techniques

IDDQ Design for Testability

Module Outline

Section Outline

Design for Testability Techniques

Ad Hoc Design for Testability Techniques

Ad Hoc Design for Testability Techniques (Cont.)

Ad Hoc Design for Testability Techniques (Cont.)

Ad Hoc Design for Testability Techniques (Cont.)

Structured Design for Testability Techniques

Level Sensitive Scan Design (LSSD)

LSSD (Cont.)

LSSD Design Rules

LSSD Advantages/Disadvantages

Random Access Scan

Boundary-Scan

Boundary-Scan Cell

Boundary-Scan Cell Modes

Boundary-Scan Chip Architecture

PCB with Boundary Scan

Boundary-Scan Test Modes

Boundary-Scan Test Modes(Cont.)

Boundary-Scan Test Modes(Cont.)

Boundary-Scan Advantages/Disadvantages

Module Outline

Section Outline

Built-In Self TestDefinitions

Built-In Self Test Definitions (Cont.)

Test-Pattern Generationfor BIST

Pseudorandom TestGeneration LFSRs

Maximal Length LFSR

LFSR Canonical Forms and Characteristic Polynomials

Signature Analysis

Signature Analysis (Cont.)

Signature Analysis Example

Multiple Input Signature Register

Built-In Logic Block Observer (BILBO)

BILBO (Cont.)

BILBO Testing

BIST Case Study - TMS32010 Data Path

BILBO Scheme

Single Signature Testing Scheme

MISR Scheme I

MISR Scheme II

Test Case Results

Autonomous Built-In Self-Test (ABIST)

Memory BIST Overview

Self-Testing System Architecture

Generations of Test Solutions

Benefits of ESTA

Benefits of ESTA (Cont.)

Module Outline

Hierarchical Design For Test

Hierarchical DesignFor Test (Cont.)

Hierarchical DesignFor Test (Cont.)

Module Outline

Synthesis for Test

Elements of Synthesis for Test

Gate-Level Synthesis for Test

Gate-Level Synthesis for Test (Cont.)

RTL Synthesis for Test

Module Outline

Section Outline

DFT Standards

DFT Standards (Cont.)

IEEE Std. 1149.1 Standard Test Access Port and Boundary-Scan Architecture

TAP Controller State Diagram

Test Logic Operation: Data Scan

IEEE Std. 1149.1b BSDL

IEEE Std. 1149.1b BSDL (Cont.)

IEEE Std. P1149.5 Standard Module Test and Maintenance (MTM) Bus Protocol

MTM-Bus Signals

MTM Protocol Layers

Module to MTM Test Bus Translation

IEEE Std. 1029.1 Waveform and Vector Exchange Specification (WAVES)

IEEE Std. 1029.1 WAVES (Cont.)

MIL-HDBK-XX47 Testability Analysis Handbook

MIL-HDBK-XX47 (Cont.)

Module Outline

Lockheed Martin ATL DFT Methodology

ATL DFT MethodologyTerms and Definitions

ATL DFT MethodologyAdditional Terms and Definitions

Relationship of Test Requirements, Test Strategies and Test Architectures

Relationship of Test Requirements, Test Strategies, and Test Architectures across Packaging Hierarchy

Test Strategy Diagram (TSD)

Test Strategy Diagram (Cont.)

ATL DFT Methodology in the RASSP Methodology

ATL HW Testability Architecture

RASSP Concepts which DFT Leverages

Benefits of Integrating DFT into RASSP

Design-For-Test Integration Tasks

Module Outline

Summary

References

References

Home Page: http://www.cedcc.psu.edu/ee497i/

Other information:
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