Slide 13 of 173
Notes:
For most ASIC designs, the typical practice is to begin with the designer’s functional verification test set. This set of vectors is then fault simulated to determine its fault coverage. If it is too low to be acceptable, more functional vectors can be added to exercise the portions of the circuit where the undetected faults lie. Another, perhaps more efficient, approach used is to feed the list of undetected fault to an Automatic Test Pattern Generation program to develop test for them.
Another approach used to to apply Design for Test or Built-In Self-test techniques as part of the design process. IBM’s use of Level Sensitive Scan Design is a famous example.
