Slide 29 of 173
Notes:
This fault model considers paths in the circuit and tests to see if any path delays exceed some DPmax. This algorithm overcomes a potential problem with the transitional fault mode. That is, that the delay of a faulty gate can be compensated by gates in the propagation path that have faster-than-typical delays.
This delay fault model is also consistent with a statistical design philosophy. A statistical design philosophy recognizes that the delays of gates in a circuit are usually not all worst case, but that they fall within a small “typical” range. Using this knowledge, a greater clock speed can be specified by determining the typical delays for all paths in the circuit.
This delay testing method is a form of performance verification. What difference does it make if a single gate is out of tolerance if the paths delays are within DPmax?
