Slide 35 of 173
Notes:
This slide shows the overall flow of the test generation process. The process begins by generating a list of all possible faults in the circuit under test. One of these faults is selected for test generation. ATPG is performed to generate a test for this fault. Once the test is generated, fault simulation is performed to determine all of the faults that are detected by that vector. These detected faults are removed from the global fault list. Another undetected fault is selected from this list and the process begins again. The loop is exited when all of the faults are either detected or have an ATPG performed unsuccessfully on them (aborted).
