Slide 42 of 173
Notes:
The Ad-Hoc test generation technique (as previously presented) uses the functional verification vectors as the initial manufacturing test vectors. They are fault simulated to determine fault coverage and undetected faults. If ATPG is not used, then the designer must add functional vectors to the test set to try and achieve higher fault coverage.
This may be especially difficult for synthesized designs because the designer doesn’t have the circuit area to behavior correspondence; i.e., he/she may not know what portion of the functionality corresponds to the undetected fault area.
