Slide 51 of 173
Notes:
The sequential ATPG process is usually modeled as a combination of 4 processes. The first is combinational ATPG for the target fault on the combinational logic block. The second, state justification, is the process of finding a sequence of inputs that will drive the state machine from the reset (or unknown) state to the Present state required by the test above. The third, state differentiation, is the process of finding an input sequence which will cause a different output sequence for the machine in the good state and faulty state as a result of the test found in the first step. And lastly, because the state justification and differentiation processes are typically done using the information about the fault-free machine, the fourth process, sequential fault simulation, is required to determine if the resulting input sequence is in fact a test for the target fault as well as other faults.
