Slide 61 of 173
Notes:
Here is an example of parallel fault simulation on a AND gate with four faults being injected. The resulting word on the output shows that the faults in the 3rd and 5th bit position have been detected (B s-a-1 and C s-a-1). This can be automatically determined by XORing each bit in the output word with the good circuit value (bit position zero)
