Slide 63 of 173
Notes:
This figure illustrates the deductive fault simulation process for a NOR gate. First, forward simulation is performed to determine all of the good values on the inputs and outputs. Then, using these values, the list of all faults that cause changes in the output are “deduced” from the input values and the gate function.
In this case, only faults that cause the values on input A to change (to “1”) without causing the values of inputs B or C to change (to “0”), will cause the output to change. Also, the faults within the logic element itself that cause the output to change must be considered. Thus, the list of faults visible on the output D is as shown above.
