Slide 65 of 173
Notes:
In this example the linked lists used in concurrent fault simulation are illustrated. In the upper circuit, the faults A s-a-0, and D s-a-0 affect the input/outputs of the AND gate and appear at the node D, These faults also effect the node E and thus appear in the linked list for that node along with C s-a-0 and E s-a-0.
If line A changes to a value of “0”, the linked list at D changes to drop fault A s-a-0 and D s-a-0 and add faults A s-a-1, B s-a-1, and D s-a-1. Since C is still ‘1’, these appear in the linked list for node E as well although the the faults C s-a-0 and E s-a-0 are dropped and the fault E s-a-1 is added.
