Slide 73 of 173
Notes:
This figure shows the effect of a defect in terms of a gate-source short in the P transistor of an inverter. When the input voltage goes low such that this transistor turns on, significant current flows between the source and gate such that IDDQ increases dramatically. However, because the gate output goes high as it should, traditional stuck-at fault testing would not detect this defect.
If the defect doesn’t affect function, why be concerned about detecting it? The answer is that the defect may be such that after a certain operating time, it will cause the device to fail, causing a detectable fault and thus an error.
