Slide 89 of 173
Notes:
This figure shows the general configuration for of a level sensitive scan design latch as well as a NAND/NOT implementation.
D is the normal data line and C is the normal clock line. Line L1 is the normal output. Lines I, A, B and L2 form the shift portion of the latch. I is the shift data in and L2 is the shift data out. A and B are the two phase, non overlapping shift clocks.
