Table of Contents
Synthesis Using VHDL RASSP Education & Facilitation Module 60 Version 1.2
RASSP Roadmap
Module Outline
Module Outline
Module Outline (Cont.)
Module Outline (Cont.)
What is Synthesis ?
Steps in the Synthesis Process
Graphical Methods
Language-based Methods
Language-based Methods (Cont.)
Steps in Synthesis (Cont.) Language-based Specification Methods
Synthesis Steps (Cont.)
Steps in the Synthesis Process (Cont.)
Steps in the Synthesis Process (Cont.)
Steps in the Synthesis Process (Cont.)
Steps in the Synthesis Process (Cont.)
Module Outline
VHDL Support for Synthesis
Design Capture
Design Specification
Design Simulation and Verification
Design Documentation
Levels of Synthesis
Synthesis Categories
Levels of VHDL-Based Synthesis
Behavioral Synthesis
Behavioral Synthesis (Cont.)
RTL Level Synthesis
Logic Synthesis
Behavioral Synthesis
Behavioral Synthesis Example (Cont.)
Input to Behavioral Synthesis
Input in Behavioral VHDL
Results from Behavioral Synthesis
Results from Behavioral Synthesis (Cont.)
Characteristics of Behavioral Synthesis
RTL Synthesis
RTL Synthesis Example
RTL VHDL Input
Characteristics of RTL Synthesis
Logic Synthesis
Summary of VHDL-Based Synthesis
Module Outline
IEEE Support for Synthesis
VHDL Packages for Synthesis Arithmetic Packages
IEEE Synthesis Packages
VHDL Packages for Synthesis Base Types
VHDL Packages for Synthesis Base Types (Cont.)
VHDL Packages for Synthesis Base Types (Cont.)
IEEE 1076.3 Package
IEEE 1076.3 Package (Cont.)
IEEE 1076.3 Package (Cont.)
IEEE 1076.3 Package (Cont.)
IEEE 1076.3 Package (Cont.)
IEEE 1076.3 Package (Cont.)
IEEE 1076.3 Package (Cont.)
IEEE 1076.3 Package (Cont.)
IEEE 1076.3 Package (Cont.)
IEEE 1076.3 Package (Cont.)
IEEE 1076.3 Package (Cont.)
Module Outline
IEEE RTL VHDL Subset
IEEE 1076.6 Definitions
Terminology
Predefined Synthesis Types
Verification Methodology
Verification (Cont.)
IEEE 1076.6 Keywords
VHDL RTL Keywords
VHDL RTL Syntax Key
RTL VHDL Types
VHDL RTL Synthesis Scalar Type
RTL Scalar Types
Composite Types
RTL VHDL Declarations
Type Declarations
Object Declarations
Supported Attribute Declarations
Component Declarations
RTL VHDL Expressions & Operators
Operators
Operators (Cont.)
Operators (Cont.)
Sequential Wait Statement
Sequential Assert/Report
Sequential Signal Assignments
Signal Assignment Examples
Variable Assignment
If Statement in Synthesis
Case Statement in Synthesis
Loop Statement in Synthesis
Loop Examples in Synthesis
Sequential Loop Statements
Miscellaneous Sequential RTL Statements
Concurrent Statements
Block Statement in Synthesis
Process Statement in Synthesis
Process Examples
Process Statements Example
Process Statements Incomplete Sensitivity List
Sequential Signal Assignment Statements
Concurrent Signal Assignment
Signal Assignment Examples
Concurrent Signal Assignment Statements
Conditional Signal Assignment Statements
Selected Signal Assignment Statements
Concurrent Procedure Call
Structural VHDL
Component Instantiation
Structural VHDL And-Or-Invert Example
Structural VHDL And-Or-Invert Example
Structural VHDL And-Or-Invert Example
Structural VHDL AOI Results
Generate Statement
Design Entities in Synthesis
Entity Syntax in Synthesis
Architecture Syntax
Configuration Syntax
Subprograms
Procedures and Functions
Procedures and Functions (Cont.)
Procedures and Functions (Cont.)
Using Procedures and Functions
Using Procedures and Functions (Cont.)
Package Syntax
Module Outline
Synthesis with RTL Subset
Combinational Circuits
VHDL in Combinational Circuits
Examples of Logic/Arithmetic
Multiplexer/Demultiplexer
Multiplexer/Demultiplexer (Cont.)
Arithmetic Logic Units (ALU)
Registers and Clocks
Clock Edge Specification
Clock Edge Specification (Cont.)
Synthesizing Flip Flops using “if”
Inferring FFs Using “if”
Inferring FFs Using“wait”
Edge Sensitive D Flip-Flop
Edge Sensitive D Flip-Flop (Cont.)
Inferring Latches
Avoiding Latches
Inferring Latches in Complex Behaviors
Synthesizing Asynchronous Signals
Inferring Level-Sensitive Logic
Level Sensitive D Latch
Synchronous RTL Synthesis Example
Synthesis of State Machines
VHDL Coding of an FSM: Example
Structure of the VHDL Description
FSM in IEEE RTL VHDL
ENUM_ENCODING OF FSMs
Sequential Datapaths
Sequential (RTL) Datapaths Example - 8 Bit Multiplier
Sequential RTL Datapaths Example - 8 Bit Multiplier
Sequential RTL Datapaths Example - 8 Bit Multiplier
Sequential RTL Datapaths Example - 8 Bit Multiplier
Sequential RTL Datapaths Example - 8 Bit Multiplier
Sequential RTL Datapaths Example - 8 Bit Multiplier
Sequential RTL Datapaths Example - 8 Bit Multiplier
Sequential RTL Datapaths Example - 8 Bit Multiplier
Sequential RTL Datapaths Example - 8 Bit Multiplier
Sequential RTL Datapaths 8 Bit Multiplier - Results
Module Outline
Optimizations Used in Synthesis
Optimization of Behavioral VHDL
Input/Output Scheduling
Operation Scheduling and Assignment
Scheduling Options During Synthesis
Scheduling Options (Cont.)
Register Allocation
Loop Pipelining
Memory and I/O Inferencing
FSM (Controller) Generation
RTL Level Optimization
Logic Level Optimizations
Module Outline
Coding Guidelines for Synthesis
Design Process Issues
VHDL Modeling Issues
VHDL Modeling Guidelines (Cont.)
Simulation Speed Issues
Simulation Speed Issues
Synthesis Modeling Issues
Synthesis Modeling Issues
Synthesis Modeling Issues (Cont.)
Synthesis Modeling Issues (Cont.)
Technology Dependence in Synthesis
Implementation Technology Considerations
Signal Selection in VHDL (for FPGAs)
Memory Design for in VHDL FPGAs
Module Outline
Summary
References
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