OBJECTIVE: The aim of this tutorial is to help
get a quick-start on synthesizing a behavioral design using Synplify. We first create a
schematic for both the ripple-adder and the Carry Look-Ahead Adder behavioral models of
the HW#2 assignment and then use the Cadence (verilog) simulator, namely VERILOG-XL to do
a "high-fidelity" simulation of the resulting synthesized circuit. We would do both functionality and timing
simulation.
It is not meant to be an in-depth tutorial for the tools
involved for the above-mentioned process, but will serve as a guideline for the basic
steps involved in simulation.
STEP 0
Before you start, ensure that your
VHDL source code is in your present working directory. Also ensure that from this present
working directory, you can access both the synplify
and also the Cadence syslab system design tools
(and associated verilog circuit simulator).
Note that, as you would see later,
its not really required to use the PIC design flow to convert the netlist file (that
Synplify generates) to the verilog file that the simulator needs. But it’s a useful
description of the kind of design flow that one normally goes through in a typical
simulation.
STEP 1 (SYNTHESIS):
In this step we will use the synplify tool to generate the schematic of the
Ripple Adder and the Carry Look-Ahead Adder.
Type "synplify " at the
command prompt. This will bring up the
Synplify
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Figure 1
· Click on the ADD button. A pop-up window will appear. Select the appropriate VHDL source file (*.vhd,
*.vhdl). In this case, the source file is
ripple_behavior.vhd.
· Click on the CHANGE button below the
Target field. A pop-up window will appear
(figure 2). Select the appropriate FPGA and
the associated options (In our case, the FPGA manufacturer is XILINX, the series is
XC4000E and the particular chip is XC4005E with a PC84 package). Note that the result file field will show a file
name with an extension .xnf for the Xilinx target option, once the appropriate target has
been selected. It is wise to force GSR usage
(global set/reset usage) for the purpose of creating a simulation model. Note that the
dark portion in the selection portion for ‘Force GSR Usage’ means that it has
been selected. Click OK when done. (Don’t worry about the Target M! Place and Route.
We are not doing place and route as of now).
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Figure 2
· Hit the large RUN button of Figure 1.
Watch as the large letter in red
shows the various stages of synthesis. If there are errors or warnings double-click on the
errors/warnings and observe the messages and make appropriate changes. If there are no errors/warnings, the synthesis is
done.
To view the RTL (structural) view of the synthesis, pull down the
HDL ANALYST menu option from the menu-bar and select the RTL_VIEW. This will show the structural synthesis as shown
in Figure 3 below.
In order to
verify the functionality and timing of the resulting synthesized circuit, the Synplify
should write out Verilog netlists after synthesis. This can be done at the Option menu item, and selecting ‘Write Mapped
Verilog Netlist’ option.
Figure 3
You can also view the
‘Technology View’ from the HDL Analyst menu.
STEP 2
Go to the terminal window and
type syslab.
The following SYSTEM DESIGN SOLUTION window should show up as shown in Figure 4
below.
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Figure 4
Click on the DIGITAL SIM icon in Figure 4 and the window will
change to appear as shown in Figure 5 below.
Click on the
SETUP icon above (i.e. Figure 5), and the following window should pop-up.
Figure 6
For
the design option, in the prompt enter the name of the xnf file (without the extension!)
generated by Synplify (in our case, ripple_behavior).
Click on time_units button located on the left side of the window in figure 6 and enter
"100ps" (without the quotes). This
sets the minimum simulation time to 100ps (the lowest possible).
Click
on the compiler button located on the left side of the window shown in figure 6. The window shown in figure 7 (below) will pop-up.
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Figure 7
In the compile type field, delete
"logic" and enter "backplane" (without the quotes). Hit APPLY and then quit.
From the window shown in figure 6,
click "global" button located on the left side of the window. The window shown in figure 8 (below) should
pop-up.
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Figure 8
In the root drawing field of the window in figure 8, enter the name of the xnf file generated by Synplify (without the extension; in our case, ripple_behavior). DO NOT QUIT THIS WINDOW, YET!!
Select the Library button from the Global window (Figure 8) and the screen shown in Figure 9 below will appear. Enter the libraries as shown in Figure 9; use the Add button to add each new library. Click on Done when you are finished.
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Figure 9
Next, click on the USE side-button of
the window in Figure 8 and Figure 10 comes up. Enter the following work directory (this
directory is used by Concept Schematic tool). Hit
done.
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Figure 10
Now, in the
window of figure 8, hit APPLY (VERY IMPORTANT) and then quit.
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Figure
11
Now, from the window in Figure 5 [Digital Simulation], click on the ASIC/PIC DESIGN button and select PIC design and then Xilinx design. The window in Figure 6 should now appear as shown in Figure 11.
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Figure
12
Wait a few seconds till you see the messages shown in the message sub-window of the window in figure 11.
Click
on SETUP in Figure 11. The window shown in figure 12 (above) should appear. Modify the
settings in your window to the one shown in Figure 12.
In
this case, we want to import the xnf file generated by Synplify. The constraints file is
needed for placing the pad locations. It is
very important to de-select "generate netlist" option. Also, provide the correct path for importing the
xnf file. Once done, hit done and the window in figure 12 will close. Now in the window
shown in figure 11, click on the NETLIST button. Now
the tool will try to import the specified xnf file. If
successful, the message-subwindow in the window shown in figure 11 will show that the
netlist import step was successful.
To generate a simulation model, keep
on reading and performing the tasks.
Click on the SimModel iconized button
of the window in figure 11. It will take
considerable time to generate the simulation model and so please be patient. Wait till the message sub-window of the window in
figure 11 shows that the step was successful. It
will beep when it is done. In case of errors,
it will tell that there were errors. In case
of errors, refer to the appropriate files indicated in the message sub-window and try to
identify and correct errors.
THE SIMMODEL CREATES THE STIMULUS
FILE ripple_behaviorf.stim CORRESPONDING TO FUNCTION SIMULATION.
ALTERNATE WAY OF CREATING THE VERILOG FILE FROM THE NETLIST FILE
THAT SYNPLIFY GENERATES: -
We will
need the .xnf file that Synplify has generated. This file should be located in the
xilinx.run directory.
The steps in the next section describe the optional command-line method of running the simulator. You may wish to skip to the next_section below.
At a Unix prompt (the place where you
have your .xnf files as well as your .vhd files), type the following command: -
Prompt> funcnet ripple_behavior.xnf
4000e -sim
where the –sim option instructs
funcnet to create a Concept body, apart_cn file, a verilog simulation model, and a
RapidSIM simulation model for the input xnf file.
The general format of the instruction
is
Prompt> funcnet file_xnf
device_arch options
where, device_arch is the target
family of our design, in our case we had selected xilinx 4000e. and options are the options for the funcnet command.
A
file by name verilog.v file should be located in a directory by name
/ripple_behaviorf/verilog_lib. Copy that file to the same directory where the stimulus
file ripple_behaviorf.stim is located.
At the Unix prompt, type the following command:
Prompt>funcsim verilog.v ripple_behavior.stim 4000e
The general syntax for funcsim is :-
Prompt>funcsim file.v file.stim
device_arch options
where
options are the Verilog-XL options.
To see the Verilog-XL options , enter verilog at the command prompt.
The .stim file is the stimulus file
that is created by ‘funcnet’ command or by the SIMmodel in the design flow.
Once the funcsim command is executed,
the window changes to as shown in Figure 13.
Figure 13
Type ? for help and follow
the instructions mentioned.
There is an alternate method of doing functional and timing simulation. Click on the ‘Digital Sim’ icon in Figure 11, and this leads to Figure 5. We can complete the simulation from the ‘Simcontrol’ icon in Figure 5.
If there are compilation errors at
this stage, then you can look at cmplog.dat and cmplst.dat files in your directory. You
can create the cmplst.dat by typing ‘comperr’ from your UNIX prompt.
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Figure 14
In the window of figure 5,
click on the wave-view button. The window shown in Figure 15 (below) should appear. It will not have the signals and waveforms
Figure 15
In the window of Figure 14, click on
START/STOP and select "START SIM". This
will prepare wave-bench for simulation of the design. After it is done, at the scl>
prompt of the command sub-window of the window in Figure 16, "open" the ports
for simulation waveview by typing
open ‘a_in<0>’;
open ‘a_in<1>’;
open ‘a_in<2>’;
and so on. Do it for all the bits of
a_in, b_in and also c_out.
You could use the abbreviation o for
‘open’. Also
open ‘a_in’;
open ‘b_in’;
open ‘c_out’;
so
that you could see the byte values either in decimal or in hexadecimal format (depending
on the radix).
The semi colon and the quotes for the
open command are to be noted.
To force a particular signal high or
low, we can enter the following command:
force ‘a_in<0>’, 1;
We could also force the entire 8-bit vector a_in by
Force ‘a_in’, 222
Force ‘b_in’, 6
and this would assign (if the radix
is 10) the decimal 222 value to a_in and 6 to b_in.
To simulate for a particular duration
of time, we can enter the following command:
sim 140ns;
which will simulate the design for
140 ns from the present simulation time.
Once all the ports have been
"opened", forced to appropriate values, the signals shown in Figure 16 should
appear.
Figure 16
For more help on this simulation tool
and commands please refer to OpenBook. IT IS
ALSO POSSIBLE TO WRITE A SCRIPT FILE TO PERFORM A BATCH SIMULATION RATHER THAN HAVING TO
ENTER THE COMMANDS ON THE COMMAND LINE.
If you wish to print your signals, issue the File > Hardcopy > Screen command after following the instructions on this link.
For immediate help, click on the help
button of the window in Figure 15.
With this, we have completed a
quick-start of Syplify, from behavioral synthesis to P&R, bit-download on the actual
FPGA and also the simulation of the synthesized model.
There are lots of options and
features and capabilities but for now, this should be more than enough to get an initial
grasp on RAPID PROTOTYPING.
Created by K.Gourishankar
(after modifications of Tarak’s Tutorial): Oct 1999
