The Pennsylvania State University

Administrative Information: this web site contains legacy information from a prior offering of EE497i (Fa`99). This class has been removed from the Fall 2000 schedule since Dr. Landis has resigned his Penn State appointment to assume his current position at the Pittsburgh Digital Greenhouse. The course information will remain here until it is removed by Penn State; please browse and enjoy.
Course Outline: Pre-req's, Topics, Grading, etc.Class Schedule, UNIX Lab, and Support / Contact Info. |
IEEE D&T Rapid Prototyping Issue |
![]() |
ANNOUNCEMENTS -- Final Exam Monday 12/13, 2:30-4:20. A study guidelines / review for the final exam is linked here. See the Examples page for VHDL Model Code examples. |
![]() |
HOMEWORK ASSIGNMENTS -- solution to Homework Assignment (#4). Take this link for the VHDL Synthesis w/ Xilinx Place & Route Quick-Start tutorial |
| READING ASSIGNMENTS -- 11/22/99 - READ RASSP Module 43 (Test Technology Overview) for the 11/23 lecture . | |
| TUTORIALS -- Instructor generated, RASSP E&F, and other presentation / reference material | |
![]() |
UNIX Lab, CAD Tool, and CADENCE -- Follow this link for CAD Tool Help, Tutorials, & FAQs. Check out the new information regarding CAD tool commands & the EE Unix Lab. |
| FPGA and RAPID PROTOTYPING LINKS -- links to RSP resources on the WWW |
This page has been viewed
times, and was last meddled with:
10/15/04
Please report all problems to - D. Landis