EE497i -- Rapid System Prototyping

Final Exam Review Materials

(overview, reading assignment, example problems)

Fall Semester `99 -- Dr. David L. Landis

Exam Date:  Monday December 13, 1999 (2:30-4:20pm, 101 EEW)

In-Class, 110-minute Exam, Closed TEXT, Closed Notebook / notes, TWO (2)  8.5" X 11" reference pages may be brought into class.

The following is a summary of the reading assignments and WWW class home page links containing information relevant to the mid-semester exam. Where appropriate, specific subsets of the materials are identified.  An important study / review hint -- make sure that you understand and can solve all mid-term exam and quiz problems.  For those questions which were commonly missed, I may repeat the same problems may create quite similar problems for the final.

• Introduction to Rapid System Prototyping -- this is the overview presentation from the first week of class. We covered the first half of the material in depth, and I highlighted the technology specific (Xilinx, etc) material in the second half of the presentation
• Programmable Logic and Application Specific Integrated Circuits -- review this .pdf file carefully for information regarding ASIC and FPGA design styles, capabilities, costs, and other tradeoffs. You should understand the technology capabilities, design styles (FPGA, MPGA, SC, FC) , cost and complexity issues, and You need not worry about the specifics of the detailed tabular listings of ASIC vendors, chip models and types, and other associated commercial chip information. 
• Be sure to review the problem statement from Homework #1, and understand any corrections that need to be made in your solution.  In particular, be familiar with Rent's Rule (here is the summary info. distributed), and with the Triangular Cost Model (I feel like I've beaten this to death already... don't worry about any new questions related to cost modeling).
• Designing Top-Down ASICs and FPGAs with Cadence Tools -- this cadence document is worth reviewing, not for the specific details of how to use the "HDLDesk tools, but for the overview of the top-down design methodology for ASICs and FPGAs.
• Be sure that you understand the VHDL basics (RASSP Module 10) and behavioral modeling (RASSP Module 12).   Also, be familiar with the Module 60 VHDL Synthesis issues discussed in class on 10/14 and 10/19.  I will not expect you to "write a complete VHDL program" as part of the exam.  However, I will be testing your understanding of VHDL.  Expect some multiple-choice problems which ask you about VHDL modeling, and perhaps some sample VHDL programs for which you have to:  1.) determine the states on the signals after a model executes, 2.)  identify any (blatant) errors in a given VHDL model (I won't be asking you to look for missing parenthesis), 3.)  fill in some missing code statements to complete a VHDL model.   link to some example VHDL problems.
• Don't forget to review your class notes on Power Consumption (as a function of FPGA speed, number of outputs, and capacitive load).  Also, don't forget about the material covered in class regarding output slew rate, skew, simultaneous output switching, and power-supply rail collapse.

RASSP Instructional Module reading assignments -- material covered prior to the mid-semester exam.

• Module 10 -- VHDL Basics -- this is the RASSP Basic VHDL module which describes the language-based top-down rapid prototyping design process. Study this module carefully -- expect some VHDL-related questions to come directly from material in this module.
• Module 12 -- Behavioral VHDL -- you should review this module, especially as it relates to the work you did in Homework Assignments 2.  It offers behavioral modeling material which supplements that found in Module 10.  In particular, make sure that you understand the distinctions between behavioral and structural modeling.
• Module 29 -- RASSP Methodology Overview -- Only a few of the slides from this module were discussed in class (this module was not assigned for reading). You should review just the information we covered relating to hardware design and virtual prototyping (and skip over the software design and hardware/software co-design segments of the presentation).
• Module 57 -- Cost Modeling for Embedded Systems -- again, we only covered a small fraction of this module in class, and used some of the material as a point of departure for classroom discussion. Don't study this module in great depth, however, if I were you I'd be sure I knew how to use the triangular cost model that is described herein. 
• Module 60 --VHDL Synthesis -- this module offers a reasonable introduction to Behavioral Modeling for VHDL Synthesis.  Review the portions of this module that were highlighted in class on Thursday 10/14.  In particular, you should know about the IEEE1164 standard and the 1076.3 and 1076.6 standard activities.  Refer to the information contained in this module, as well as that contained on the VHDL International web-site (see links on the class home page).
• Module 43 -- Test Technology Overview Module -- This module covers testability and design for test. Of particular interest is the Design for Test and Synthesis for Test, and Test Standards sections. We spent several class periods reviewing the test and DFT issues, and it's fair to assume that the final exam will contain questions relating to this material -- especially review the quiz #4 material and example questions from the prior final exam.

Xilinx Information: specific details of the Xilinx families of FPGAs and their relevant architectural features are contained in the 3-day University seminar slides. Now is a good time to review this Xilinx info. When you're studying the RASSP Testability Module (43), it would also be a good idea to review the IEEE1149.1 (JTAG) features and capabilities of the Xilinx 4000 family standard parts.

Altera Information: You should go right to the Altera WWW site for information of their architecture and chip options. Be sure to look over the specifics of the FLEX 10K Embedded Array internal architecture as well as the MAX family design which was discussed in class.

Other Reference Materials may get linked here...

• Example Mid-Semester Exam from a previous semester (Fall 1998 EE497i Mid-Semester Exam) -- don't forget to go back and look at the power-consumption problem (#15) now that we have covered this material in class.
• Example Final Exam from Spring 1998 -- (EE497i Final Exam).  Note that a few questions are not relevant to the current semester (e.g. we didn't study the TI DSP paper), however much of the material is quite relevant to the current semester.