CURRENT HOMEWORK ASSIGNMENT (HW#4)

LATE BREAKING UPDATES --  Note, in the HW4 tutorial, we correctly identify in the Synplify Menu that the "Target M1 Place and Route tools" box should be checked in order to complete place - route - download of your design to the evaluation board.  HOWEVER, this box should NOT be checked when running Synthesis if the goal is to do Syslab (VerilogXL) timing simulation.  Leaving this box unchecked will target the Foundation tools which Cadence / Syslab needs for correct simulation.

I told you in class tuesday (11/30) that my "sine wave output" didn't seem to be correct when I showed you the DDFS running on the Xilinx Evaluation Board.  It turns out that the design is fine, but my observation was flawed.  YOU SHOULD NOTE that the LEDs connected to the Xilinx chip will illuminate when the output is LOW, and will be extinguished when the output is HIGH.  This produces the effect of a logic inversion when you view your outputs!  In order to make the LED results display in true form, I simply added a final statement to my model (dout <= NOT sine)

SECONDARY NOTE:  some of you only used a 1/4 sine wave table in your HW #3 solution.  This is incorrect (although I didn't give out penalties for this error, in part because my posted example from the ).  However, in HW#4 I expect you to correctly store the entire sine (or cosine) table from 0 degrees through (63/64 * 360) degrees.   For example, you could use a positive encoded sine wave with data points every 5.625 degrees e.g. sin(0) = 0 = (100000), sin(90) = 1 = (111111), sin(270) = (-1) = (000000), etc.  Alternatively, you could use a 2's complement encoded output as illustrated by the FSK modulator DDFS design posted on the examples page (although it is a bit less intuitive to view a 2's complement result on the eval. board LEDs).

Instructions for Homework #4 submission:

Part A -- hard-copy submission -- the usual thing -- brief text description (a paragraph or two), followed by ANNOTATED print-outs of your design documentation as follows:  hard copy of VHDL model, test bench, leapfrog simulation results, syslab (verilog XL) timing simulation results (draw conclusion regarding the max. clock frequency of operation, and compare to the max. frequency predicted by synplify in the <design_name.srr> report).  

Part B -- electronic submission -- send me an email message (dll2@psu.edu) with two attachments:  one being your VHDL model, and the second being your .bit file which successfully downloads to the eval board.  In the body of the email message, give me any special instructions regarding how to operate your design (or indicate if there are features of the design which are not working correctly).  If you don't get to the stage of successfully generating the download file, don't bother to send email; simply turn in your (partial) hardcopy results.

Use the following file-naming convention:  <account_name>_hw4.vhd and <account_name>_hw4.bit  For example, I would name my files:  dll2_hw4.vhd and dll2_hw4.bit.

This is the final version of Homework Assignment #4; details of this problem are as follows: 

In Homework assignment #3 you designed (VHDL-Behavioral), simulated (using Leapfrog),  and synthesized, a coherent Direct Digital Frequency Synthesizer.  In homework assignment #4 you will modify your DDFS design so that it can be downloaded and demonstrated on the Xilinx Evaluation board in the lab.  Your design must be revised as follows:

• Reference Clock Frequency = 20MHz (available on the Evaluation board as a crystal controlled reference clock on pin 13 of the XC4005EPC84 FPGA).

• The internal phase accumulator of your design will utilize a 29-bit adder and phase register (so that you can produce a low enough frequency to observe as digital outputs on the evaluation board LEDs.

• Your design will use the 8 available dip switches (SW3) to control the 29-bit phase accumulator input as follows:   The least significant 7 bits of the frequency selection input will be connected to the least significant 7 switches.  The most significant bit switch will control the remaining 20 inputs (i.e. the upper 20 bits of frequency input will be all 0's of all 1's according to the state of the MSB dip switch)

        Pin assignments for the 8 dip switches are as follows:

• S/N Ratio of output sine wave >36db ==> 2^6 X 6-bit Sine look-up table.  The 6-bit output will be connected to the right-hand six LEDs of the Evaluation board's bar-graph display.

        Bar graph LED pin assignments are as follows:

The Homework #4 Quickstart tutorial is available here. It covers Synthesis, simulation, place & route, and downloading your design to the FPGA Demo Board

[Take this link to view the (Fall `98 legacy) Synplify VHDL Synthesis, and take this link to the (Fall `98 legacy) Xilinx M1 tool Place / Route / Download  Quick-Start tutorial.]

Note the new command added to the EE497I Cadence page, hwdebug.  This command can be used to run the Xilinx Hardware Debugger for downloading your FPGA .bit file to the demo board.  Note that the hardware debugger is also available from directly within the Xilinx M1 tool.  The M1 tool is started by the command xilinx at the UNIX prompt.

The hardware manual for the Xilinx FPGA Demo Board is available in PDF format here. (Large 1.2M file)

Also, see this link to setup your Waveview printing environment for the EE Labs.

Completed Homework & HW Assignment Reference Links
(Non-Current Assignment information postings will remain here throughout the semester 

Homework Assignment #3 is now posted (here is the link). 

1. synthesize and simulate ripple-carry and fast adder designs from HW#2.  Compare and contrast the two designs in terms of their complexity and speed of operation.

2. design (VHDL-Behavioral), synthesize, and simulate a coherent Direct Digital Frequency Synthesizer which meets the following specs:

   • Maximum Frequency of Operation: 16+ MHz

   • Frequency Resolution 1Hz

   • S/N Ratio of output sine wave >36db

Take this link to view the VHDL Synthesis Quick Start Tutorial

• Design Project Preliminary Design Review (PDR) due Tuesday 11/2/99.  Maximum of 5 pages.   Required PDR project elements:

  1. System description -- definition of your design project in the "system context".  Essential to provide a system block diagram, with explanatory text.

  2. Design Plan:  partitioning of the problem, block diagrams of components / sub-components

  3. Development and demonstration plan -- what will you design first, what next?  how will you simulate and verify functionality and performance

  4. Identify Deliverables -- results and final report -- how will you know when you're done?

• Homework Assignment Number 2 -- This homework assignment was posted on Thursday 9/23/99 -- this is the first VHDL modeling and simulation assignment using Cadence and the SUN/UNIX lab.   This assignment is due on Thursday October 7th, 1999.
• Homework Assignment Number 1 This homework assignment has been released in final form.  Your Homework Solution must include detailed prototype design style, density, and packaging recommendations for maximum system profit (include all supporting mathematical/graphical justification for your recommendations).  This homework is due on September 16, 1999.
• Follow this link to RASSP Module 57 -- Cost Modeling for Embedded Digital Systems. This presentation covers the Triangular Cost model and other information relevant to the homework assignment -- this material will be presented in the 9/7 and/or 9/9 lecture.
• PowerPoint (Intro. to Rapid System Prototyping) Slides used for 8/26 and 8/31 class lectures.
• Supplemental material to the PowerPoint slides: "ASICs & Programmable Logic" This book chapter portable document format (.pdf) file provides background for the 9/1 and 9/3 lectures, and for Homework Assignment #1
• Supplemental Reading - Brief 5-page Overview and Summary of Rents Rule (E.F. Rent, IBM, 1960) from Chapter 9 of "Circuits, Interconnections, and Packaging for VLSI" by H.B. Bakoglu, Addison Wesley, 1990

The instructions below will lead you through the Leapfrog VHDL compilation and simulation step with an example Flip-Flop model.  Once you have successfully navigated this Quickstart tutorial, you will be ready to complete your HW#2 assignment.

Leapfrog VHDL Quickstart guide: Follow these instructions to bring up Leapfrog, set up your libraries, compile a sample VHDL model, and simulate the model.  Note that this guide uses a Flip-Flop VHDL model example, which is given below.  Cut and paste from Netscape into your text editor to generate the VHDL source file and test bench file.

•  Part - I:  Compiling the code

•  Part - II: Simulation  --  

•  The Flip-Flop model that goes with the Tutorial -- Sample VHDL behavioral model for testing the Leapfrog simulator, 

• The Test bench for the Flip Flop model  -- Sample VHDL test bench for testing the Flip-Flop

• Block Diagram (figure1) of the Example Flip-Flop

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Last Meddled With: 10/15/04 - D. Landis