-- VHDL SYNTAX ISN'T CASE SENSITIVE AND SO I HAVE USED CAPITALS FOR
-- THE KEY VHDL WORDS

-- THE CODE STARTS BELOW....
 

-- INTERFACE DESCRIPTION:
-- the interface description begins with the keyword ENTITY
-- In the interface description, we will provide the interface
-- using the keyword PORT.  The keyword GENERIC provides the generic
-- parameters can be used to segregate the physical and design-specific
-- characteristics of a particular technology or ambient conditions.
-- Bottomline, generics provide a means of passing on non-hardware
-- and non-signal  information between designs.
-- The values provided in the GENERIC declaration are default values
-- These values can be forced to some other values by explicitly "mapping"
-- them to new values (...in a later example...) the same way a port
-- is mapped (..in the next file accompanying this file..)

ENTITY flop IS
 GENERIC (td_reset, td_in : TIME := 8 NS);
 PORT( qout : OUT BIT; reset, din, clk : IN BIT);
END flop;

--
-- We will now provide a behavioral description of our flip-flop.
-- Basically, what we are doing is describing the architecture of a
-- flip-flop.  The architecture is a behavioral description and so we
-- will term it as ARCHITECTURE behavioral.  We can as well name it
-- xyz but that can cause confusion in interpreting.
-- The ARCHITECTURE belongs to some entity; in this case it is flop and
-- hence the name 'flop' after OF

ARCHITECTURE behavioral OF flop IS
-- We now begin the description of the architecture...
BEGIN
-- We are going to provide a sequential description of the behaviour
-- The sequential statement body is contained in a "PROCESS".
-- The sequential statements are executed when the flow of the program
-- reaches it.
-- Normally the PROCESS statement is always active and it executes at
-- all times.  If we want to suspend the process, we can declare
-- a sensitivity list.  In the following example, clk is a parameter in
-- the sensitivity list.  The Process statements are executed only
-- when an event occurs on the signals/parameters mentioned in the
-- sensitivity list.  In the example, whenever a clock transition occurs
-- the process statements will be executed.  After executing all the
-- process statements, the process will be suspended till another
-- clock transition.
 PROCESS(clk)
 BEGIN
-- Look at the statement IF; it is similar to most software languages..
-- An important attribute is the 'EVENT attribute.  S'EVENT returns a
-- boolean value.  It returns true if an event just occured on signal S
-- Otherwise it returns a False.  So, our IF statement looks for the
-- following: if the clock is '0' after an event (in our case, a
-- transition).  This means if it was the falling edge of the clock.
-- I think the rest of the IF statement is pretty much apparent.

  IF(clk = '0' AND clk'EVENT) THEN
   IF reset='1' THEN
    qout <= '0' AFTER td_reset;
   ELSE
    qout <= din AFTER td_in;
   END IF;
  END IF;
 END PROCESS;
END behavioral;
 

-- That completes our basic example!!  For those who aren't familiar
-- with "task scheduling" i.e. transactions, please try to understand
-- transactions because that is a very important concept in VHDL
-- simulation (and unlike any softaware language that i have used like
-- PASCAL or C or FORTRAN...).
-- FEEL FREE TO CLEAR YOUR DOUBTS!

-- In the next example, we will simulate our VHDL model.  For this
-- purpose, we will create a "test-bench" code and apply stimuli
-- to our model and look for the response from the model.