-- Declaring the entity:
-- notice that there are no ports for the testbench.
-- Refer to figure 1. to get an idea of the model of
-- the test bench.  Go back to the previous link and
-- follow the "testbench Model" link.

ENTITY flop_test_bench IS
END flop_test_bench;
 

-- Architecture description.
-- The architecture will be called test_bench because that
-- is what it is!

ARCHITECTURE test_bench OF flop_test_bench IS

-- the following line delares the "component" being used.
 COMPONENT flp1 PORT( qout: OUT BIT; reset ,din ,clk: IN BIT); END COMPONENT;

-- the following statement says that the a1 instance of flp1 should use
-- the behavioral description of flop entity
 FOR a1: flp1 USE ENTITY work.flop(behavioral);

-- The following statements declare the signals in the test_bench
 SIGNAL reset1 : bit;
 SIGNAL din1 : bit;
 SIGNAL clk1: bit;
 SIGNAL qout1 : bit;

-- the statement part of the test_bench.

 BEGIN

-- The following statement "instantiates" a1 and associates signals
-- to the flop entity (since flp1 was to use the flop entity).
  a1: flp1 PORT MAP(qout1, reset1, din1, clk1);

-- the following statements simply create waveforms for the signals.
  clk1 <= '1' AFTER 0 NS, '0' AFTER 10 NS,
   '1' AFTER 20 NS, '0' AFTER 30 NS,
   '1' AFTER 40 NS, '0' AFTER 50 NS,
   '1' AFTER 60 NS, '0' AFTER 70 NS,
   '1' AFTER 80 NS, '0' AFTER 90 NS,
   '1' AFTER 100 NS, '0' AFTER 110 NS;
  reset1 <= '0' AFTER 0 NS, '1' AFTER 50 NS;
  din1 <= '1' AFTER 0 NS, '0' AFTER 20 NS,
   '1' AFTER 40 NS, '0' AFTER 60 NS,
   '1' AFTER 80 NS, '0' AFTER 100 NS,
   '1' AFTER 120 NS;
END test_bench;
 

-- That was the test bench to test the flop model.  The test
-- bench shown above is a simple one; for very large test benches,
-- there are more efficient ways to create a test-bench.