EXAMPLE PROBLEM # 2
 
Note:  This problem is not a solution to the homework #2.  The only similarity it has with the homework problem is the absence of any clock timing or data synchronization information.

PROBLEM DEFINITION:  Write a VHDL behavioral description for a serial-to-parallel converter.  The converter should take every 4 consecutive bits and present them as parallel output.  The converter should have a single input port and four bit-output ports to present the parallel data.  As of now, there are no details available about synchronization or timing of the data.

A possible Solution:
 
The Black-box Interface
 
        The input is serial data. Normally the serial data will by synchronous, but we don't have any information about the clock or when the data on the input serial line has changed.

        We are to group every 4 consecutive bits and once we get 4 consecutive bits, we are to push them out in parallel.

        Notice that we don't have any information on the synchronization. We are not supposed to use any generic that might relate to clock period.
 
        A possible solution to the problem definition is provided below.  Please feel free to refer to it or use your own methods.  Also feel free to modify and the structures and experiment.  Please be noted that this is just one of the possible solutions to the example problem statement.  THIS IS NOT A SOLUTION TO HOMEWORK #2 !!!


A NOTE ON TRANSACTION, EVENT AND SOME ATTRIBUTES:

A Transaction and an Event:  Whenever a value v is scheduled to be assigned after delay d, a transaction is said to have been scheduled.  Suppose this transaction is scheduled at time 'to'.  Then at time t = to + d, the value v will be assigned to the signal.  At this point, a transaction is said to have been completed.  If the new value v is same as the old value of the signal, no change in the value takes place and no event has said to have occured.  If, however, the value v is different from the old value, the value of the signal will change at time t = to+d and an EVENT is said to have occured.
        It is possible to have multiple transactions scheduled for a signal; and in this case, the various transactions have to be resolved.  Please refer to a text on VHDL to understand the resolution of transactions.

Transaction Attribute: This is a signal kind of type bit that toggles each time a transaction occurs on the signal with which it is associated.  Example: x<= s'TRANSACTION  .  Whenever a transaction completes on s, the value of the signal s'TRANSACTION will toggle and this value will be assigned to the signal x.  Note that x has to be defined as a signal kind of type bit.

Event Attribute: Example s'EVENT .  This is a value of boolean type.  The value will be TRUE if in a simulation cycle the value of s changes.

Other Attributes: Some other attributes are DELAYED, STABLE, LAST_EVENT, LAST_VALUE, QUIET, ACTIVE, LAST_ACTIVE, DRIVING, DRIVING_VALUE.  Please look them up for understanding what they are.


VHDL FILES:

Black-box Entity Architecture: Click here to view the VHDL source file. Our black box will be called s2d.

Test-Bench File: Click here to view the VHDL test-bench file for testing the s2d behavior.

Output Waveform: To understand the waveform below, please read the comments in both the VHDL files mentioned above.  The output bit-vector value will depend on your initial conditions during simulation.  So don't be surprised to see a different pattern.  Notice the A1:Din signal.  The individual 1's and 0's show the instances when new serial data has been introduced on the signal.


 
 

Note: No stress was given on creating an "optimal" or "good" VHDL code. The aim is to show how timing details/synchronization details can be ignored while creating an abstract behavioral model.

Last updated: 2/7/1998. - Tarak