RASSP Methodology Overview Module 29 RASSP Education & Facilitation Program M29_01_00 August 1997

1/15/98


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Table of Contents

RASSP Methodology Overview Module 29 RASSP Education & Facilitation Program M29_01_00 August 1997

Rapid Prototyping Design Process

Module Goals

RASSP Methodology Overview Outline

RASSP Methodology Overview Outline

RASSP Methodology Overview Outline

RASSP Technical Approach

RASSP Methodology

RASSP - How It Relates to Methodology

RASSP - How it Relates to Methodology (Cont.)

RASSP Methodology

RASSP Design Concepts and Enablers

Iterative Virtual Prototype - the "Spiral" Model

“Spiral” Methodology Chart

RASSP Methodology Overview Outline

Detailed Section Outline

Detailed Section Outline (Cont.)

Conventional Design Process

Current Practice

System Definition

System Definition (Cont.)

Hardware Design

Hardware Design (Cont.)

Software Design

Software Design (Cont.)

Hardware/Software Integration

Detailed Section Outline

Proposed Approach

Rationale for New Process

RASSP Target

Features and Limitations of Existing Codesign Methodologies

Detailed Section Outline

RASSP Methodology: Virtual Prototyping

Representation of a RASSP System

Virtual Prototyping

Other RASSP E&F Modules of Interest

Definitions

Virtual Prototyping Should Provide the Following

Detailed Section Outline

Virtual Prototyping Executable Req./Spec.

Executable Requirements and Specifications

Benchmark SAR Executable Requirement

Goals of Processor

Goals of the Test Bench

Elements in Executable Specification of the System Model

Relationship Between Executable Requirements and Specifications

Detailed Section Outline

Virtual Prototyping

Data/Control Flow Modeling

Data/Control Flow Graph Generation

Flow Graph Generation and Simulation Mechanism

Detailed Section Outline

Virtual Prototyping

Embedded-System HW/SW Design, Integration and Test

Autocoding

Automated System-level Design Environment

HW/SW System Prototyping Costs

The Effect of Packaging on Prototyping Costs

REVIC Software Development Cost/Schedule Model

REVIC Software Development Cost/Schedule Model

Design Example: SAR Processor Requirements

Dependence of Objection Functions on Customer Class

SAR Multiprocessor

Manual Tradeoffs

Design Tradeoff Case Study: SAR Processor with COTS Multiprocessor Cards

Detailed Section Outline

Performance Modeling

Architecture Selection Process

Performance Modeling in System-level Design

SCI (IEEE Std 1596-1992) Component Elements

SCI (IEEE Std 1596-1992) Multiprocessor Performance Simulation

Scalability Tradeoffs

Performance Modeling of SAR Processor

Detailed Section Outline

Virtual Prototyping

Virtual Prototyping at the Fully Functional and Detailed Levels

Virtual Prototyping: Fully Functional Level

Efforts in HW/SW Integration and Test Relative Benefits

Simulation Performance vs Fidelity

Case Study: Design IRST System Prototype

Case Study IRST: System Tests

Case Study IRST: System Tests (Cont.)

Case Study IRST: System Tests (Cont.)

Case Study: MCV9 Processing Boards

Case Study MCV9: Test Process

Case Study MCV9: Phase II/III Integration Tests

MCV9 Subsystem Architecture

MCV9 VHDL Creation

Case Study: i860XP RISC

Case Study i860: Functionality Breakdown

Designated Processor Tree

Case Study MCV9: Subsystem-level Test

Case Study MCV9: Phase I Integration Objectives

Case Study MCV9: Phase II/III Integration Objectives

Case Study MCV9: Timing Diagram of RACEway Write

Case Study MCV9: Simulation Results

Case Study IRST: Simulation Results

Case Study IRST: HW/SW Integration

Detailed Section Outline

Section Outline

Model Year Chart

Model Year Architecture

Model Year Architecture

RASSP Model Year Architecture within the Design Process

HW/SW Codesign - Key Part of Model Year Architecture

Components of Model Year Architecture

Model Year Architecture Approach

High-Level Functional Architecture

Interface Approach

Functional Interface Example Applied to RNI

Approach to Standard Virtual Interface (SVI)

Guidelines for Using SVI

Applications of SVI

Implications of Layering

Design Guidelines and Constraints

Architectures for Testability

Design For Test Tasks

Test Architecture

Test Architecture (Cont.)

Software Overview

Software Architecture Process Goals

Software Architecture Requirements

Software Architecture

Software Architecture (Cont.)

Software Architecture (Cont.)

Software Architecture (Cont.)

Software Architecture (Cont.)

Software Architecture Diagram

RASSP Graph-Based Software Development Scenario

Detailed Section Outline

What Is a Re-use Data Element?

What is a Re-use Data Elements? (Cont.)

How Re-use Fits into RASSP

Contents of Reuse Library

Library Population

RASSP Methodology Overview Outline

Results to Date

IRST Virtual Prototyping Results

Results to Date

RASSP Methodology Overview Outline

Preliminary ARPA Assessment

Summary: Addressing System Level Design Enables Achievement of 4x

Summary

Exercises

References

Author: Tom Egolf

Email: dll2@psu.edu

Home Page: http://www.cedcc.psu.edu/

Other information:
RASSP E&F Program Slides used by PSU -- EE497I Rapid System Prototyping