Cost Modeling for Embedded Digital Systems Design Module 57
PPT Slide
Module Outline
Module Outline (Cont.)
Motivation for Cost Modeling in the Design Process
Complexity of the Design Space for Embedded Systems
Typical Prototyping Process Flow
Example for Modeling Software Development Cost/Time
Execution Time, FE, and Main Storage Constraint, FM, Effort Multipliers
Cost Impact of Schedule Compression/Extension
Effect of HW Resource Constraints on HW/SW System Prototyping Costs
Design Trade-off Example: SAR Processor with COTS Multiprocessor Cards
Potential Effect of Packaging on Prototyping Costs
Effect of HW Resource Constraints on Schedule
Effect of Schedule Delays on Time-to-Market Cost
Triangular Time-to-Market Cost Model
Economic Cost-Driven System-Level Design
Overall Library-Based System Design Methodology
Cost Committed Over the Product Life Cycle
Cost-Driven Front-End Design Process
Basic Software Cost Estimation Process
Software Estimation Risks
Parametric Models
Information Needed to Use a Parametric Model
REVIC
Additional Project Attributes for REVIC
Summary of SW Cost Estimators
Classifications of Design and Test Methodologies
Case Study: SAR Multiprocessor
SAR Algorithm: Single Polarization
Functional Decomposition
SAR System-Level Cost Parameters
SAR Software Cost Driver Ratings
Automated Cost-Driven Architecture Design (RACEWAY)
SAR Architectural Profiles
SAR Benchmark Cost Analysis
Cost Improvement: Methodology II over I
Cost Improvement: Methodology II over I (Cont.)
Cost Improvement: Methodology II over III
Cost Improvement: Methodology IV over I
Cost Improvement: Methodology IV over III
Cost Improvement: Methodology V over I
Cost Improvement: Methodology V over III
Summary
Summary (Cont.)
References
References (Cont.)
Home Page: http://www.cedcc.psu.edu/ee497i/
Other information: RASSP E&F Copyrighted Presentation Materials For non-profit educational use only by the Penn State EE497I Rapid System Prototyping Class