CURRENT READING ASSIGNMENT

11/22/99 - READ RASSP Module 43 (Test Technology Overview) for the 11/23 lecture -- this will be a good source of material for the fourth (and final) quiz next week.  Emphasis as per discussion in class (Overview only of first 80 slides -- testability issues and terminology, stuck-at fault models, purpose of fault simulation, etc.  In-depth consideration of Design for Testability, BIST, etc. in the second half of the module)  

11/4/99 -- Xilinx Technology-Specific Reading Assignment: an overview of specific details of the Xilinx families of FPGAs and their relevant architectural features are contained in their 3-day University seminar slides (see links below). Full and up-to-date details are contained in the Xilinx Databook -- study the XC4000 Product Family chapter of the "databook.pdf" file, or go on-line to the Xilinx Website for the XC4000E FPGA Family DataSheet.  Also, don't forget to look up the differences between the various XC4000 family parts (4000, 4000a, 4000E, 4000XL, 4000XV). Specific and up-to-date information about the entire Xilinx product line is available here. When you study the RASSP Testability Module (43), it will also be a good idea to review the IEEE1149.1 (JTAG) features and capabilities of the Xilinx 4000 family standard parts.

Xilinx University Seminar Day 1 -- Xilinx University Seminar Day 2 -- Xilinx University Seminar Day 3

PAST READING ASSIGNMENTS

• 10/7/99 -- VHDL Synthesis (RASSP Module 60)
• 9/18/99 -- VHDL Behavioral Modeling (RASSP Module 12)
• 9/21/99 -- VHDL Overview - RASSP Module 10. Use this link for a high resolution "frames" version of this "Introduction to VHDL" presentation - Beginning with the 9/14/99 class we will introduce the VHDL language, within the context of using VHDL as a design tool.  
• General VHDL Reference and Tutorial Information -- this is a link to all EE497I class-specific VHDL reference information and materials, as well as to RASSP program instructional materials (VHDL Introduction, Structural - Behavioral - System Level Modeling, and Synthesis).
• 8/24/99 Reading Assignment -- Introduction to Rapid System Prototyping -- these are the PowerPoint Presentation slides used for 8/26 and 8/31 class lectures. They provide an introduction to rapid system prototyping concepts in general, and to the EE497I class topics in specific.
• Week of 8/30/99 Reading Assignment -- Programmable Logic and Application Specific Integrated Circuits - WARNING -- 284K Adobe Acrobat (.pdf) File... This link provides background material about the digital hardware implementation technologies and options available for rapid system prototyping. This is a draft of my chapter from the 1996 Active Electronic Component Handbook. Most of the material had been reproduced faithfully in this conversion, but some figures are missing. Refer to the McGraw Hill publication (ISBN 0-07-026692-1) for the full text, figures, and many other chapters of useful electronics reference material.
• 9/2/99 -- Follow this link to RASSP Module 57 -- Cost Modeling for Embedded Digital Systems. We will discuss the part of this presentation which covers the Triangular Cost model and other information relevant to the homework assignment -- this material will be presented in the 9/7  lecture. We will discuss the part of this presentation which covers the Triangular Cost model and other information relevant to the homework assignment -- this material will be presented in the 9/7  lecture.

GENERAL READING ASSIGNMENT info. (current and "legacy" links):

• EE497I VHDL Reference and Tutorial Information -- this is a link to all EE497I class-specific VHDL reference information and materials, as well as to RASSP program instructional materials (VHDL Introduction, Structural - Behavioral - System Level Modeling, and Synthesis).
• RASSP Module 60 - Synthesis Using VHDL - use this link for a normal view of the slide presentation, or select this link for frames at high resolution.
• RASSP Module 12 - Behavioral VHDL - use this link for a normal view of the slide presentation, or select this link for frames at high resolution.
• VHDL Synthesis Links -- here is a link to information regarding the IEEE P1076.6 VHDL Synthesis Interoperability Working Group standards activity page.  Also of interest on the "VHDL International" web server is some IEEE 1164 standard information in the form of the Numeric Standard itself.   While you're at the VHDL International web site, be sure to check out their Links pages.
• VHDL Quick Reference Guide -- from the Doulos VHDL Training Web Pages (a brief and concise VHDL reference card)
• Introduction to Rapid Prototyping - PowerPoint presentation introducing rapid system prototyping concepts in general and the EE497I class topics in specific.
• Programmable Logic and Application Specific Integrated Circuits - WARNING -- 284K .pdf File... This link provides background material about the digital hardware implementation technologies and options available for rapid system prototyping. This is a draft of my chapter from the 1996 Active Electronic Component Handbook. Most of the material had been reproduced faithfully in this conversion, but some figures are missing. Refer to the McGraw Hill publication (ISBN 0-07-026692-1) for the full text, figures, and many other chapters of useful electronics reference material.
• PowerPoint (Intro. to Rapid System Prototyping) Slides used for 9/1 and 9/3 class lectures.
• Supplemental material to the PowerPoint slides: "ASICs & Programmable Logic" This book chapter portable document format (.pdf) file provides background for the 9/1 and 9/3 lectures, and for Homework Assignment #1
• Supplemental Reading - Brief 5-page Overview and Summary of Rents Rule (E.F. Rent, IBM, 1960) from Chapter 9 of "Circuits, Interconnections, and Packaging for VLSI" by H.B. Bakoglu, Addison Wesley, 1990

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Last Meddled With: 10/15/04 - D. Landis