VHDL Behavioral Description for SYNERGY tutorial

For the tutorial, we will be using the following code:
 
                ENTITY example IS
                 PORT( clock, a, b, sel : IN BIT; d : OUT BIT);
                END example;

                ARCHITECTURE behavior OF example IS
                begin
                 PROCESS(clock)
                 BEGIN
                  IF(clock'EVENT AND clock = '1') THEN
                   IF(sel = '1') THEN d <= a OR b;
                   ELSE d<= a AND b;
                   END IF;
                  END IF;
                 END PROCESS;
                END behavior;

(Figure 1)
The behavior of the code in figure 1 is apparent, however for the purpose of clarity, the following test bench was used to simulate the code:
 
                ENTITY test_bench IS
                END test_bench;

                ARCHITECTURE tester OF test_bench IS
                 COMPONENT unit1 port(clock, a, b, sel : IN BIT; d : OUT BIT);
                 END COMPONENT;
                 
                 FOR a1: unit1 USE ENTITY work.example(behavior);
                 SIGNAL clock, a, b, sel, d : BIT;
                 
                BEGIN

                 a1: unit1 PORT MAP(clock, a, b, sel, d);
                 
                 clock <= '0' AFTER 0 NS, '1' AFTER 1 NS,
                          '0' AFTER 2 NS, '1' AFTER 3 NS,
                          '0' AFTER 4 NS, '1' AFTER 5 NS,
                          '0' AFTER 6 NS, '1' AFTER 7 NS,
                          '0' AFTER 8 NS, '1' AFTER 9 NS,
                          '0' AFTER 10 NS, '1' AFTER 11 NS,
                          '0' AFTER 12 NS, '1' AFTER 13 NS,
                          '0' AFTER 14 NS, '1' AFTER 15 NS,
                          '0' AFTER 16 NS, '1' AFTER 17 NS,
                          '0' AFTER 18 NS, '1' AFTER 19 NS,
                          '0' AFTER 20 NS, '1' AFTER 21 NS,
                          '0' AFTER 22 NS, '1' AFTER 23 NS,
                          '0' AFTER 24 NS, '1' AFTER 25 NS;
                          
                 sel <= '0' AFTER 0 NS, '1' AFTER 9.5 NS;
                 a <= '0' AFTER 0 NS, '1' AFTER 5.5 NS,
                      '0' AFTER 10.5 NS, '1' AFTER 15.5 NS;
                 b <= '0' AFTER 0 NS, '1' AFTER 2.5 NS, '0' AFTER 4.5 NS,
                      '1' AFTER 6.5 NS, '0' AFTER 8.5 NS, '1' AFTER 10.5 NS,
                      '0' AFTER 12.5 NS, '1' AFTER 14.5 NS, '0' AFTER 16.5 NS,
                      '1' AFTER 18.5 NS;

                END tester;    

The following figure provides visual information on the behavior of the code using the above mentioned test-bench.
 
 


Link to Part-I of the SYNERGY tutorial