FIGURE 1.5

FIGURE 1.6

FIGURE 1.7

Preserve Boundary:  This command identifies objects-either design units, instances or functions-that are to be synthesized and optimized seperately from the rest of the design.  This constraint applies only to the objects specified, not to the objects constrained within them.  To apply the preserve-boundary constraint downward through the design heirarchy, use the -tree option.
    When preserving the boundary of a design unit, Synergy is prevented from removing or modifying the heirarchial boundaries of all instances of that design unit.  However all instances of that design unit are the same.
    When preserving the boundary of an instance, Synergy synthesizes and optimizes that instance seperately from the rest of the design.  That instance might be different from other instances of the same design unit because it is optimized for its particular context.
    When preserving the boundary of a function, the function is transformed into an object that is referenced as an instance.
    When preserving the boundary of an object, one can also specify an optimization alternative, including normal, mapping, drive optimization or resizing.  Logic structuring of the design includes decomposition and partition of the design, technology-independent optimization and canonoical graph optimization.
 
Options for Preserve-Boundary: Alternatives:
    normal: Synergy performs logic structuring, technology mapping, design rule checks and buffer optimization and this is default.
    Mapping: Synergy performs technology mapping, design rule checks, and buffer optimization.  This option is useful when one includes preoptimized or custom designed cells in a macro-library or in the design or when one has modelled datapath alogrithms at the equation level.
    Critical Path Resynthesis: Synergy identifies the critical path or paths in the design andthen preserves and reoptimizes only the critical circuit nodes in that path.  Non-critical nodes are preserved.  One can compare the results from re-optimization with the original synthesis of that circuit.
    DriveOpt: Synergy performs design rule checks and buffer optimization.  With this option, Optimizer attempts to correct maxfanout and timing violations in an existing netlist by rebuilding buffer trees and replacing existing gates of different size but identical function.  One can use this to map a netlist from one vendor to another or to repotimize a netlist with new constraints or with back-annotated wire loads.  The input design must be a structural netlist.

MAINTAIN:
This command identifies design units, instances, variables and signals in the design that are not to be synthesized or optimized.  The maintain constrain causes Synergy to pass the objects specified into the synthesized netlist without modifications.
    This command applies only to the objects specified, not to the objects contained within them.  To apply the maintain constraint downward through the design heirarchy use the -tree option.
    When a design unit is maintained, all the instances of the design unit are prevented from being synthesized.  The original design unit definition and all instances appear in the HDL netlist without change.  When one sets a maintain constraint on an instance, the instance and its contents are prevented from being synthesized.  However other instances of the design unit that are not specified are synthesized.

EXPAND:
    This command flattens the design object into the parent object and then synthesizes and optimizes them together.  One can apply this constraint to design units as well as instances.  The -tree option should be used to apply the constraint downward through the design heirarchy.
 

For this tutorial, select Preserve boundary.

From the Options field, select the design unit/instance only (in this example, we don't have a tree structure and so it makes no sense in selecting that option).

We want to initially optimize for timing.  So select Timing with Min Cost.  By doing so, Synergy will synthesize for minimum cost and then slowly increase the cost to try and meet the timing specifications.  The cost in case of Synergy is Area (number of components).

Don't close the window!!  Hit apply first and then close the window.  These constraints should appear in the Constraints sub-window of the Synergy window (figure (1.2, 1.5).

4. ENTERING OPTIMIZATION CONSTRAINTS:
 Click on the hour-glass icon in the Synergy Window.  This should open the window shown in figure 1.8 below.  The window will open with the clocks tab as the default tab.
 

FIGURE 1.8

 
Here we will enter the clock constraints.  We have used a clock in our design and so we will identify the clock by selecting the appropriate signal from the clock pull-down tab (next to the Define in figure 1.8).  In our design, we have used the signal clock as the clock signal for our design.  Now in the rise, enter 0, in the fall enter 25 and in the period enter 50 (the default units are nanoseconds).  Thus, we have defined our clock as having 50 % duty cycle with a period of 50 nanoseconds.  Hit Apply.  DO NOT HIT CLOSE.

Now select the wires/ports tab from the window shown in figure 1.9.  The figure shown in figure 1.10 will appear.
 
 

FIGURE 1.9

The side-tab should be global.  These are the default values for the inports and outports and input-output ports (buffer ports).  Leave the input fields empty.  In the Output, we want our output port constraints to be defined relative to the clock "clock".  So, in the Relative to clock field, select the clock signal (in our case, in this design we have only one clock and so that will be the clock selected automatically when clicked).  Enter the value of 7 (7 nanoseconds, that's our specification). in the required rise/fall entries as shown in figure 1.9.  Hit apply.

To get a sense of the rise/fall maximum/minimum timing values, look at the figure 1.10 provided below.  More details can be obtained by hitting the help button.   Basically, the minimum/maximum rise times provide a "window" during which the signal is expected to rise (i.e. basically change value for going high) and similarly, minimum/maximum fall times provide a "window" during which the signal is expected to fall (i.e. change value for going low).  If the maximum = minimum, then that is the desired time (rise or fall).  In this example, we have said that we want the rise and fall times to be 7 (maximum=minimum).  No tolerance (window) allowed.
 
 

FIGURE 1.10

Now we will specify the input constraints (we could as well have done this by entering the values through the input field in the global side-tab but that's okay as we will specify these constraints specifically for all inputs via the input-side-tab).

Click on the INPUT side-tab and the window shown in figure 1.11 should appear.
 

FIGURE 1.11

The inputs are relative to the positive edge of the clock and so select the edge field and the clock signal from the "relative to clock" entries as shown.  We hypothesize that our inputs A, B and SEL will appear 3 ns earlier than the positive edge of the clock (as these inputs are externally controlled).  So just enter -3 ns in the rise/fall entry fields as shown.  If the hypothesis is not a good one, we can modify them as required.  Hit apply.

Now select the outputs tab.  The window shown in figure 1.12 should appear.
 
 

FIGURE 1.12

 

As can be seen, the entries in global field have already been applied to our output signal D.  If these values aren't quite as desired, we can change them.  This output side-tab allows us to supply specific parameter constraints for each output.

We will not enter any fan-in/fan-out or load optimization parameters as this tutorial is meant to provide a first-grasp on Synergy.

The entry "enable timing path" is very important.  We have mentioned that the optimization is for speed with minimum cost.  If we disable the timing path, all paths related to the signal (input/output) get labelled as non-critical paths and so are ignored by Synergy during optimization.  All our inputs are related to the output (the only output D in our example) and so we want to enable the timing paths of all the inputs and outputs (by default this is selected on and so it is already taken care of).

Hit apply.

We don't have any wire-models nor do we have input/output (buffer) ports and so we can ignore the two side-tabs.

Hit close.

Now we have entered all the optimization parameters for a first run of synthesis (if after optimization we find that the synthesis is not quite to our satisfaction or that our requirements are too stringent, we can do a second run after re-entering the optimization parameters).

With this, we are all set for the synthesis/optimization run.  Refer to Part-III of this tutorial for details about that.

HELP BUTTONS IN EACH SUB-WINDOW PROVIDE DETAILED INFORMATION ABOUT VARIOUS ENTRIES!
PLEASE REFER TO THE HELP BUTTONS FOR MORE INFORMATION!!!