SYNERGY TUTORIAL - PART IV
Link to Part III of the tutorial 

After completing the steps mentioned in the previous three parts, at this stage, there will be numerous VHDL files and synthesis report files.  We haven't yet generated any schematic and so those files will not be present.

The important files to be looked at are the contraints report, timing report and area report.  However, these reports include the use of signals and "objects" (by objects i mean the additional signals/gates/wires that Synergy has added in synthesizing the design).  So it would be helpful to take a look at the netlist/schematic.  Schematic is graphical and so it is much more easier to read than a netlist.  However this may not be always true for very large designs where it may be impossible to look below modules.

Anyway, for understanding, first let me list the netlist generated by Synergy:


NETLIST GENERATED BY SYNERGY:

library ieee;
use ieee.std_logic_1164.all;

package pack_example_behavior_syn is

    function stdl_to_bit(oper : std_logic) return bit;

end pack_example_behavior_syn;
 

package body pack_example_behavior_syn is

    function stdl_to_bit(oper : std_logic) return bit is
    begin
        return(to_bit(oper));
    end stdl_to_bit;
 

end pack_example_behavior_syn;
library ieee;
use ieee.std_logic_1164.all;
 

--------- Netlist Entity Declaration --------
 

entity example_struct is
    port (
           clock : in std_logic;
           a : in std_logic;
           b : in std_logic;
           sel : in std_logic;
           d : out std_logic);
end example_struct;
 

--------- Netlist Architecture Body ---------

library xc4000e_syn;
use xc4000e_syn.xc4000e_syn_decl_pack.all;
architecture behavior_syn of example_struct is
    signal w7 : std_logic;
    signal w6 : std_logic;
    signal w0 : std_logic;
    signal w12 : std_logic;
    signal w11 : std_logic;
    signal w9 : std_logic;
    signal w10 : std_logic;
    signal w4 : std_logic;
    signal w5 : std_logic;
    signal w8 : std_logic;
    signal w3 : std_logic;
    signal w2 : std_logic;
    signal w1 : std_logic;

begin

 g12 : buff port map(
    o => d, i => w3
    );
 g11 : buff port map(
    o => w3, i => w7
    );
 g10 : buff port map(
    o => w7, i => w6
    );
 g9 : buff port map(
    o => w6, i => w0
    );
 g8 : buff port map(
    o => w0, i => w12
    );
 g7 : buff port map(
    o => w12, i => w11
    );
 g6 : buff port map(
    o => w11, i => w5
    );
 g5 : inv port map(
    o => w2, i => a
    );
 g4 : nor2 port map(
    o => w9, i0 => sel,
    i1 => b
    );
 g3 : nor2 port map(
    o => w10, i0 => w9,
    i1 => w2
    );
 g2 : and2 port map(
    o => w4, i0 => sel,
    i1 => b
    );
 g1 : or2 port map(
    o => w1, i0 => w4,
    i1 => w10
    );
 g0 : xgnd port map(
    ground => w8
    );
 reg_w00000369 : fdc port map(
    q => w5, c => clock,
    clr => w8, d => w1
    );
end behavior_syn;
 

--------- Envelope Architecture Body ---------

library ieee;
use ieee.std_logic_1164.all;
use work.pack_example_behavior_syn.all;
architecture behavior_syn of example is
component example_struct
    port (
           clock : in std_logic;
           a : in std_logic;
           b : in std_logic;
           sel : in std_logic;
           d : out std_logic);
end component;
begin

    vhs_m1 : example_struct
         port map (
                    clock => to_stdulogic(clock),
                    a => to_stdulogic(a),
                    b => to_stdulogic(b),
                    sel => to_stdulogic(sel),
                    stdl_to_bit(d) => d);
end behavior_syn;


Look at the architecture behavior_syn inside the netlist.  This is basically a structural VHDL listing generated by Synergy.  This netlist can be simulated in Leapfrog (but right now we are working on getting this fixed).  At the same time, if you have noticed the hammer icon (next to the synthesis icon) and explored, there are tools available to generate schematics from the netlist.

As this feature is right now being worked on, and as the example is a simple one, I have pieced together the following figure illustrating the various components used by Synergy.  It is apparent that the circuit will function as described in the VHDL description and so we are sure that Synergy has done its task as far as the functionality is concerned.


"HAND CRAFTED" SCHEMATIC FROM THE NETLIST GENERATED:

As can be seen, Synergy has put a whole bunch of buffers between signals w5 and d (output).  I have omitted the signals between w5 and d but there are 7 buffers between w5 and d.  Each buffer adds to a time delay as will be apparent by looking at the time report.

Now let us look at the time report to correlate the time report with the synthesized netlist:


TIME REPORT:

               ***********************************************
                 Cadence Design Systems, Inc.

                 Optimizer Timing Report Sorted by Arrival Time
                 Circuit: Work.example.behavior_syn
               ***********************************************

                 Time unit:   1ns.      Precision:  10ps
               ***********************************************

                 Maximum Clock Frequency = 125.000 MHz

                 Longest Path Delay  =   8.00 ns

               ***********************************************

 Longest Path :
 -----------------
  StartPin        Arr.Time        EndPin        Arr.Time          Slack
--------------------------------------------------------------------------
  sel             F( 47.00)       w1            F( 50.00    )      0.00
--------------------------------------------------------------------------

 Shortest Path :
 -----------------
  StartPin        Arr.Time        EndPin        Arr.Time          Slack
--------------------------------------------------------------------------
  clock           R(  0.00)       d             F(  8.00    )      1.00
--------------------------------------------------------------------------

               ************  Top 2 Longest Paths  ************

Arrival     Inc  Fanout  Load   Cell(pin to pin)    Instance(wire to wire)
------------------------------ Long Critical Path 1 ---------------------------
All times for the path relative to rising edge of clock: clock

F( 47.00)   0.00    2    0.00   Input_pin           sel
R( 48.00)   1.00    1    0.00   nor2(i0=>o)         g4(sel=>w9)
F( 49.00)   1.00    1    0.00   nor2(i0=>o)         g3(w9=>w10)
F( 50.00)   1.00    1    0.00   or2(i1=>o)          g1(w10=>w1)
F( 50.00)   0.00                fdc(d)              reg_w00000369(w1)

The Slack Time of Long Critical Path 1 is   0.00 ns (Req. Time:clock|r|50.00 ns)

------------------------------ Long Critical Path 2 ---------------------------
All times for the path relative to rising edge of clock: clock

R(  0.00)   0.00 <-- clock      fdc(c)              reg_w00000369(clock)
F(  1.00)   1.00    1    0.00   fdc(c=>q)           reg_w00000369(clock=>w5)
F(  2.00)   1.00    1    0.00   buff(i=>o)          g6(w5=>w11)
F(  3.00)   1.00    1    0.00   buff(i=>o)          g7(w11=>w12)
F(  4.00)   1.00    1    0.00   buff(i=>o)          g8(w12=>w0)
F(  5.00)   1.00    1    0.00   buff(i=>o)          g9(w0=>w6)
F(  6.00)   1.00    1    0.00   buff(i=>o)          g10(w6=>w7)
F(  7.00)   1.00    1    0.00   buff(i=>o)          g11(w7=>w3)
F(  8.00)   1.00    1    0.00   buff(i=>o)          g12(w3=>d)
F(  8.00)   0.00                Output_pin          d

The Slack Time of Long Critical Path 2 is  -1.00 ns (Req. Time:clock|r|7.00  ns)
 
 

               ************  Top 2 Shortest Paths  ***********

Arrival     Inc  Fanout  Load   Cell(pin to pin)    Instance(wire to wire)
------------------------------ Short Critical Path 1 --------------------------
All times for the path relative to rising edge of clock: clock

R(  0.00)   0.00 <-- clock      fdc(c)              reg_w00000369(clock)
F(  1.00)   1.00    1    0.00   fdc(c=>q)           reg_w00000369(clock=>w5)
F(  2.00)   1.00    1    0.00   buff(i=>o)          g6(w5=>w11)
F(  3.00)   1.00    1    0.00   buff(i=>o)          g7(w11=>w12)
F(  4.00)   1.00    1    0.00   buff(i=>o)          g8(w12=>w0)
F(  5.00)   1.00    1    0.00   buff(i=>o)          g9(w0=>w6)
F(  6.00)   1.00    1    0.00   buff(i=>o)          g10(w6=>w7)
F(  7.00)   1.00    1    0.00   buff(i=>o)          g11(w7=>w3)
F(  8.00)   1.00    1    0.00   buff(i=>o)          g12(w3=>d)
F(  8.00)   0.00                Output_pin          d

The Slack Time of Short Critical Path 1 is   1.00 ns (Req. Time:clock|r|7.00  ns)

------------------------------ Short Critical Path 2 --------------------------
All times for the path relative to rising edge of clock: clock

F( 47.00)   0.00    2    0.00   Input_pin           sel
F( 48.00)   1.00    1    0.00   and2(i0=>o)         g2(sel=>w4)
F( 49.00)   1.00    1    0.00   or2(i0=>o)          g1(w4=>w1)
F( 49.00)   0.00                fdc(d)              reg_w00000369(w1)

The Slack Time of Short Critical Path 2 is  49.00 ns (Req. Time:clock|r|0.00  ns)


Now it is easy to correlate the netlist generated with the timing report.  However, we are also interested in seeing the constraint results, whether our constraints were met or not.  So, now let me tabulate the constraints file:


CONSTRAINTS REPORT:

***********************************************
                 Cadence Design Systems, Inc.

                 Optimizer Max-fanout File
                 Circuit: Work.example.behavior_syn
               ***********************************************

                 Violation Tolerance =   0.00
               ***********************************************

                 Total Maximum Load Violations = 0

                 Total Maximum Fanout Violations = 0

                 Total Maximum Transition Violations = 0
 

               ***********************************************

                             Maximum Load

               ***********************************************

Constraint   Cell(pin)    Instance(wire)     Library   Actual  Viola   Status
                                              Value    Value   -tion
-------------------------------------------------------------------------------
Max load      fdc(  q)  reg_w00000369(w5      )     unspecified
Max load     Input_pin  clock     (clock   )     unspecified  <- clock signal
Max load     xgnd(ground)  g0        (w8      )     unspecified
Max load      or2(  o)  g1        (w1      )     unspecified
Max load     and2(  o)  g2        (w4      )     unspecified
Max load     Input_pin  sel       (sel     )     unspecified
Max load     Input_pin  b         (b       )     unspecified
Max load     nor2(  o)  g3        (w10     )     unspecified
Max load     nor2(  o)  g4        (w9      )     unspecified
Max load      inv(  o)  g5        (w2      )     unspecified
Max load     Input_pin  a         (a       )     unspecified
Max load     buff(  o)  g6        (w11     )     unspecified
Max load     buff(  o)  g7        (w12     )     unspecified
Max load     buff(  o)  g8        (w0      )     unspecified
Max load     buff(  o)  g9        (w6      )     unspecified
Max load     buff(  o)  g10       (w7      )     unspecified
Max load     buff(  o)  g11       (w3      )     unspecified
Max load     buff(  o)  g12       (d       )     unspecified

               ***********************************************

                             Maximum Fanout

               ***********************************************

Constraint   Cell(pin)    Instance(wire)     Library   Actual  Viola   Status
                                              Value    Value   -tion
-------------------------------------------------------------------------------
Max Fanout     fdc(  q)  reg_w00000369(w5      )     unspecified
Max Fanout    Input_pin  clock     (clock   )     unspecified  <- clock signal
Max Fanout    xgnd(ground)  g0        (w8      )     unspecified
Max Fanout     or2(  o)  g1        (w1      )     unspecified
Max Fanout    and2(  o)  g2        (w4      )     unspecified
Max Fanout    Input_pin  sel       (sel     )     unspecified
Max Fanout    Input_pin  b         (b       )     unspecified
Max Fanout    nor2(  o)  g3        (w10     )     unspecified
Max Fanout    nor2(  o)  g4        (w9      )     unspecified
Max Fanout     inv(  o)  g5        (w2      )     unspecified
Max Fanout    Input_pin  a         (a       )     unspecified
Max Fanout    buff(  o)  g6        (w11     )     unspecified
Max Fanout    buff(  o)  g7        (w12     )     unspecified
Max Fanout    buff(  o)  g8        (w0      )     unspecified
Max Fanout    buff(  o)  g9        (w6      )     unspecified
Max Fanout    buff(  o)  g10       (w7      )     unspecified
Max Fanout    buff(  o)  g11       (w3      )     unspecified
Max Fanout    buff(  o)  g12       (d       )     unspecified

               ***********************************************

                             Maximum Transition

               ***********************************************

Constraint   Cell(pin)    Instance(wire)     Library   Actual  Viola   Status
                                              Value    Value   -tion
-------------------------------------------------------------------------------
Max Trans.     fdc(  q)  reg_w00000369(w5      )     unspecified
Max Trans.    Input_pin  clock     (clock   )  clock signal
Max Trans.    xgnd(ground)  g0        (w8      )     unspecified
Max Trans.     or2(  o)  g1        (w1      )     unspecified
Max Trans.    and2(  o)  g2        (w4      )     unspecified
Max Trans.    Input_pin  sel       (sel     )     unspecified
Max Trans.    Input_pin  b         (b       )     unspecified
Max Trans.    nor2(  o)  g3        (w10     )     unspecified
Max Trans.    nor2(  o)  g4        (w9      )     unspecified
Max Trans.     inv(  o)  g5        (w2      )     unspecified
Max Trans.    Input_pin  a         (a       )     unspecified
Max Trans.    buff(  o)  g6        (w11     )     unspecified
Max Trans.    buff(  o)  g7        (w12     )     unspecified
Max Trans.    buff(  o)  g8        (w0      )     unspecified
Max Trans.    buff(  o)  g9        (w6      )     unspecified
Max Trans.    buff(  o)  g10       (w7      )     unspecified
Max Trans.    buff(  o)  g11       (w3      )     unspecified
Max Trans.    buff(  o)  g12       (d       )     unspecified
               ***********************************************
                 Cadence Design Systems, Inc.

                 Optimizer Constraint Report File
                 Circuit: Work.example.behavior_syn
               ***********************************************
 

                 Total Time Constraint Violations = 2
 

               ***********************************************
                 Cost Report
                 Circuit: Work.example.behavior_syn
               ***********************************************
 

                  Target_Value        Actual_Value     Status
               ------------------------------------------------
                  unspecified         5.000
 
 
 

               ***********************************************
                 Timing Report
                 Circuit: Work.example.behavior_syn
                 Time unit:   1ns.      Precision:  10ps
               ***********************************************
 

               ******* Required Time for Longest Paths *******

ID       Constraint             Port    Target_Value    Actual_Value    Status
------------------------------------------------------------------------------
 1  MaxRequiredRise                  d     clock|r|  7.00    clock|r|  8.00    Violated
 2  MaxRequiredFall                  d     clock|r|  7.00    clock|r|  8.00    Violated

               ******* Required Time for Shortest Paths *******

ID       Constraint             Port    Target_Value    Actual_Value    Status
------------------------------------------------------------------------------
 3  MinRequiredRise                  d     clock|r|  7.00    clock|r|  8.00      Met
 4  MinRequiredFall                  d     clock|r|  7.00    clock|r|  8.00      Met
               ***********************************************
                 Cadence Design Systems, Inc.

                 Optimizer Sequential Constraint Report File
                 Circuit: Work.example.behavior_syn
                 Time unit:   1ns.      Precision:  10ps
               ***********************************************

                 Violation Tolerance =   0.00
               ***********************************************
 

                 Total Setup Violations = 0

                 Total Hold Violations = 0

                 Total Clock Width Violations = 0
 

               ***********************************************

                             Setup Violations
               ***********************************************

               ***********************************************

                              Hold Violations
               ***********************************************

               ***********************************************

                    Clock Width Violations (rising edge)
               ***********************************************

               ***********************************************

                    Clock Width Violations (falling edge)
               ***********************************************


From the constraints file it is evident that the only constraints we specified were the timing constraints.  And these constraints haven't been met.

Also notice that the path from sel to w1 is listed as a long critical path and it takes 3 ns for the signal to propagate.  This gives me an important information that my signals a, b and sel should arrive much earlier than 3 ns than the rising edge of the clock if i want to ensure that the clock edge appears after my inputs have settled properly and can be used by the clock's positive edge.

Looking at the timing report, one can notice that there is a significant delay occuring due to the buffers.  I can only assume that Synergy tried to meet my stringent timing constraint of 7 ns (remember that i had not provided any "window" for output timing requirement) and so put in buffers to try and meet my timing constraint (if you recall in Part - II of the tutorial, i had chosen "meet the minimum timing constraint" condition in the synthesis window).

So now I might want to go back and resynthesize if the 8ns is not acceptable.  But before we go and do that, let me post the gate-count report:


STATISTICS REPORT:

***********************************************
                 Cadence Design Systems, Inc.

                 Netlist Statistics Report

                 Circuit: Work.example.behavior_syn
     ***********************************************

Total number of cells:          14
Total cell area:              5.00

Total number of inputs:          4
Total number of outputs:         1
Total number of inouts:          0

Total number of nets:           18
Total number of used pins:      33
Total number of unused pins:     0
Pins-per-net ratio:           1.83

Pin Distribution of Nets
========================
Number of    1 pin nets:       3
Number of    2 pin nets:      15

Cell Porosity Distribution
===========================
      Model        Instances    TotalTracks    BlockedTracks
------------------------------------------------------------
      and2               1           n/a             n/a
      buff               7           n/a             n/a
      fdc                1           n/a             n/a
      inv                1           n/a             n/a
      nor2               2           n/a             n/a
      or2                1           n/a             n/a
      xgnd               1           n/a             n/a
------------------------------------------------------------
Total     7             14           n/a         n/a

The above report is prettymuch self-apparent.  Notice that right now at this stage of design, we are only interested in the model parts and the number of parts used (the rest such as unused pins, porosity, tracks etc. will be of importance during layout).

Now to meet my constraints, i can go back and modify the input timing constraints and also provide a "window" for the output timing constraints.  I did not modify the input timing constraints (though it is apparent that it has to be more like -6 ns if i am to be absolutely sure).  Instead, i changed the timing constraints so that the min rise/fall was 6ns and the max rise/fall was 7 ns.

The re-optimized netlist is listed below.  If one tries to compare the netlist generated earlier with the netlist generated now, the number of buffers have been reduced.  I could have chosen other optimization techniques (critical path resynthesis etc.) and explored the results.


REOPTIMIZED NETLIST:

library ieee;
use ieee.std_logic_1164.all;
 

--------- Netlist Entity Declaration --------
 

entity example_struct is
    port (
           clock : in std_logic;
           a : in std_logic;
           b : in std_logic;
           sel : in std_logic;
           d : out std_logic);
end example_struct;
 

--------- Netlist Architecture Body ---------

library xc4000e_syn;
use xc4000e_syn.xc4000e_syn_decl_pack.all;
architecture behavior_syn of example_struct is
    signal w8 : std_logic;
    signal w2 : std_logic;
    signal w6 : std_logic;
    signal w5 : std_logic;
    signal w7 : std_logic;
    signal w3 : std_logic;
    signal w9 : std_logic;
    signal w10 : std_logic;
    signal w4 : std_logic;
    signal w0 : std_logic;
    signal w1 : std_logic;

begin

 g10 : buff port map(
    o => d, i => w8
    );
 g9 : buff port map(
    o => w8, i => w2
    );
 g8 : buff port map(
    o => w2, i => w6
    );
 g7 : buff port map(
    o => w6, i => w5
    );
 g6 : buff port map(
    o => w5, i => w4
    );
 g5 : inv port map(
    o => w7, i => a
    );
 g4 : nor2 port map(
    o => w3, i0 => sel,
    i1 => b
    );
 g3 : nor2 port map(
    o => w9, i0 => w3,
    i1 => w7
    );
 g2 : and2 port map(
    o => w10, i0 => sel,
    i1 => b
    );
 g1 : or2 port map(
    o => w0, i0 => w10,
    i1 => w9
    );
 g0 : xgnd port map(
    ground => w1
    );
 reg_w00000369 : fdc port map(
    q => w4, c => clock,
    clr => w1, d => w0
    );
end behavior_syn;
 

--------- Envelope Architecture Body ---------

library ieee;
use ieee.std_logic_1164.all;
use work.pack_example_behavior_syn.all;
architecture behavior_syn of example is
component example_struct
    port (
           clock : in std_logic;
           a : in std_logic;
           b : in std_logic;
           sel : in std_logic;
           d : out std_logic);
end component;
begin

    vhs_m1 : example_struct
         port map (
                    clock => to_stdulogic(clock),
                    a => to_stdulogic(a),
                    b => to_stdulogic(b),
                    sel => to_stdulogic(sel),
                    stdl_to_bit(d) => d);
end behavior_syn;


 REOPTIMIZED TIMING REPORT: (notice the difference in timing from the previous timing report)

***********************************************
                 Cadence Design Systems, Inc.

                 Optimizer Timing Report Sorted by Arrival Time
                 Circuit: Work.example.behavior_syn
               ***********************************************

                 Time unit:   1ns.      Precision:  10ps
               ***********************************************

                 Maximum Clock Frequency = 166.667 MHz

                 Longest Path Delay  =   6.00 ns

               ***********************************************

 Longest Path :
 -----------------
  StartPin        Arr.Time        EndPin        Arr.Time          Slack
--------------------------------------------------------------------------
  sel             F( 47.00)       w0            F( 50.00    )      0.00
--------------------------------------------------------------------------

 Shortest Path :
 -----------------
  StartPin        Arr.Time        EndPin        Arr.Time          Slack
--------------------------------------------------------------------------
  clock           R(  0.00)       d             F(  6.00    )      1.00
--------------------------------------------------------------------------

               ************  Top 2 Longest Paths  ************

Arrival     Inc  Fanout  Load   Cell(pin to pin)    Instance(wire to wire)
------------------------------ Long Critical Path 1 ---------------------------
All times for the path relative to rising edge of clock: clock

F( 47.00)   0.00    2    0.00   Input_pin           sel
R( 48.00)   1.00    1    0.00   nor2(i0=>o)         g4(sel=>w3)
F( 49.00)   1.00    1    0.00   nor2(i0=>o)         g3(w3=>w9)
F( 50.00)   1.00    1    0.00   or2(i1=>o)          g1(w9=>w0)
F( 50.00)   0.00                fdc(d)              reg_w00000369(w0)

The Slack Time of Long Critical Path 1 is   0.00 ns (Req. Time:clock|r|50.00 ns)

------------------------------ Long Critical Path 2 ---------------------------
All times for the path relative to rising edge of clock: clock

R(  0.00)   0.00 <-- clock      fdc(c)              reg_w00000369(clock)
F(  1.00)   1.00    1    0.00   fdc(c=>q)           reg_w00000369(clock=>w4)
F(  2.00)   1.00    1    0.00   buff(i=>o)          g6(w4=>w5)
F(  3.00)   1.00    1    0.00   buff(i=>o)          g7(w5=>w6)
F(  4.00)   1.00    1    0.00   buff(i=>o)          g8(w6=>w2)
F(  5.00)   1.00    1    0.00   buff(i=>o)          g9(w2=>w8)
F(  6.00)   1.00    1    0.00   buff(i=>o)          g10(w8=>d)
F(  6.00)   0.00                Output_pin          d

The Slack Time of Long Critical Path 2 is   1.00 ns (Req. Time:clock|r|7.00  ns)
 
 

               ************  Top 2 Shortest Paths  ***********

Arrival     Inc  Fanout  Load   Cell(pin to pin)    Instance(wire to wire)
------------------------------ Short Critical Path 1 --------------------------
All times for the path relative to rising edge of clock: clock

R(  0.00)   0.00 <-- clock      fdc(c)              reg_w00000369(clock)
F(  1.00)   1.00    1    0.00   fdc(c=>q)           reg_w00000369(clock=>w4)
F(  2.00)   1.00    1    0.00   buff(i=>o)          g6(w4=>w5)
F(  3.00)   1.00    1    0.00   buff(i=>o)          g7(w5=>w6)
F(  4.00)   1.00    1    0.00   buff(i=>o)          g8(w6=>w2)
F(  5.00)   1.00    1    0.00   buff(i=>o)          g9(w2=>w8)
F(  6.00)   1.00    1    0.00   buff(i=>o)          g10(w8=>d)
F(  6.00)   0.00                Output_pin          d

The Slack Time of Short Critical Path 1 is   1.00 ns (Req. Time:clock|r|5.00  ns)

------------------------------ Short Critical Path 2 --------------------------
All times for the path relative to rising edge of clock: clock

F( 47.00)   0.00    2    0.00   Input_pin           sel
F( 48.00)   1.00    1    0.00   and2(i0=>o)         g2(sel=>w10)
F( 49.00)   1.00    1    0.00   or2(i0=>o)          g1(w10=>w0)
F( 49.00)   0.00                fdc(d)              reg_w00000369(w0)

The Slack Time of Short Critical Path 2 is  49.00 ns (Req. Time:clock|r|0.00  ns)


REOPTIMIZED CONSTRAINTS REPORT:

               ***********************************************
                 Cadence Design Systems, Inc.

                 Optimizer Max-fanout File
                 Circuit: Work.example.behavior_syn
               ***********************************************

                 Violation Tolerance =   0.00
               ***********************************************

                 Total Maximum Load Violations = 0

                 Total Maximum Fanout Violations = 0

                 Total Maximum Transition Violations = 0
 

               ***********************************************

                             Maximum Load

               ***********************************************

Constraint   Cell(pin)    Instance(wire)     Library   Actual  Viola   Status
                                              Value    Value   -tion
-------------------------------------------------------------------------------
Max load      fdc(  q)  reg_w00000369(w4      )     unspecified
Max load     Input_pin  clock     (clock   )     unspecified  <- clock signal
Max load     xgnd(ground)  g0        (w1      )     unspecified
Max load      or2(  o)  g1        (w0      )     unspecified
Max load     and2(  o)  g2        (w10     )     unspecified
Max load     Input_pin  sel       (sel     )     unspecified
Max load     Input_pin  b         (b       )     unspecified
Max load     nor2(  o)  g3        (w9      )     unspecified
Max load     nor2(  o)  g4        (w3      )     unspecified
Max load      inv(  o)  g5        (w7      )     unspecified
Max load     Input_pin  a         (a       )     unspecified
Max load     buff(  o)  g6        (w5      )     unspecified
Max load     buff(  o)  g7        (w6      )     unspecified
Max load     buff(  o)  g8        (w2      )     unspecified
Max load     buff(  o)  g9        (w8      )     unspecified
Max load     buff(  o)  g10       (d       )     unspecified

               ***********************************************

                             Maximum Fanout

               ***********************************************

Constraint   Cell(pin)    Instance(wire)     Library   Actual  Viola   Status
                                              Value    Value   -tion
-------------------------------------------------------------------------------
Max Fanout     fdc(  q)  reg_w00000369(w4      )     unspecified
Max Fanout    Input_pin  clock     (clock   )     unspecified  <- clock signal
Max Fanout    xgnd(ground)  g0        (w1      )     unspecified
Max Fanout     or2(  o)  g1        (w0      )     unspecified
Max Fanout    and2(  o)  g2        (w10     )     unspecified
Max Fanout    Input_pin  sel       (sel     )     unspecified
Max Fanout    Input_pin  b         (b       )     unspecified
Max Fanout    nor2(  o)  g3        (w9      )     unspecified
Max Fanout    nor2(  o)  g4        (w3      )     unspecified
Max Fanout     inv(  o)  g5        (w7      )     unspecified
Max Fanout    Input_pin  a         (a       )     unspecified
Max Fanout    buff(  o)  g6        (w5      )     unspecified
Max Fanout    buff(  o)  g7        (w6      )     unspecified
Max Fanout    buff(  o)  g8        (w2      )     unspecified
Max Fanout    buff(  o)  g9        (w8      )     unspecified
Max Fanout    buff(  o)  g10       (d       )     unspecified

               ***********************************************

                             Maximum Transition

               ***********************************************

Constraint   Cell(pin)    Instance(wire)     Library   Actual  Viola   Status
                                              Value    Value   -tion
-------------------------------------------------------------------------------
Max Trans.     fdc(  q)  reg_w00000369(w4      )     unspecified
Max Trans.    Input_pin  clock     (clock   )  clock signal
Max Trans.    xgnd(ground)  g0        (w1      )     unspecified
Max Trans.     or2(  o)  g1        (w0      )     unspecified
Max Trans.    and2(  o)  g2        (w10     )     unspecified
Max Trans.    Input_pin  sel       (sel     )     unspecified
Max Trans.    Input_pin  b         (b       )     unspecified
Max Trans.    nor2(  o)  g3        (w9      )     unspecified
Max Trans.    nor2(  o)  g4        (w3      )     unspecified
Max Trans.     inv(  o)  g5        (w7      )     unspecified
Max Trans.    Input_pin  a         (a       )     unspecified
Max Trans.    buff(  o)  g6        (w5      )     unspecified
Max Trans.    buff(  o)  g7        (w6      )     unspecified
Max Trans.    buff(  o)  g8        (w2      )     unspecified
Max Trans.    buff(  o)  g9        (w8      )     unspecified
Max Trans.    buff(  o)  g10       (d       )     unspecified
               ***********************************************
                 Cadence Design Systems, Inc.

                 Optimizer Constraint Report File
                 Circuit: Work.example.behavior_syn
               ***********************************************
 

                 Total Time Constraint Violations = 0
 

               ***********************************************
                 Cost Report
                 Circuit: Work.example.behavior_syn
               ***********************************************
 

                  Target_Value        Actual_Value     Status
               ------------------------------------------------
                  unspecified         5.000
 
 
 

               ***********************************************
                 Timing Report
                 Circuit: Work.example.behavior_syn
                 Time unit:   1ns.      Precision:  10ps
               ***********************************************
 

               ******* Required Time for Longest Paths *******

ID       Constraint             Port    Target_Value    Actual_Value    Status
------------------------------------------------------------------------------
 1  MaxRequiredRise                  d     clock|r|  7.00    clock|r|  6.00      Met
 2  MaxRequiredFall                  d     clock|r|  7.00    clock|r|  6.00      Met

               ******* Required Time for Shortest Paths *******

ID       Constraint             Port    Target_Value    Actual_Value    Status
------------------------------------------------------------------------------
 3  MinRequiredRise                  d     clock|r|  5.00    clock|r|  6.00      Met
 4  MinRequiredFall                  d     clock|r|  5.00    clock|r|  6.00      Met
               ***********************************************
                 Cadence Design Systems, Inc.

                 Optimizer Sequential Constraint Report File
                 Circuit: Work.example.behavior_syn
                 Time unit:   1ns.      Precision:  10ps
               ***********************************************

                 Violation Tolerance =   0.00
               ***********************************************
 

                 Total Setup Violations = 0

                 Total Hold Violations = 0

                 Total Clock Width Violations = 0
 

               ***********************************************

                             Setup Violations
               ***********************************************

               ***********************************************

                              Hold Violations
               ***********************************************

               ***********************************************

                    Clock Width Violations (rising edge)
               ***********************************************

               ***********************************************

                    Clock Width Violations (falling edge)
               ***********************************************


REOPTIMIZED STATISTICS REPORT: (notice that the number of buffers have been reduced thereby meeting our constraints)

Total number of inputs:          4
Total number of outputs:         1
Total number of inouts:          0

Total number of nets:           16
Total number of used pins:      29
Total number of unused pins:     0
Pins-per-net ratio:           1.81

Pin Distribution of Nets
========================
Number of    1 pin nets:       3
Number of    2 pin nets:      13

Cell Porosity Distribution
===========================
      Model        Instances    TotalTracks    BlockedTracks
------------------------------------------------------------
      and2               1           n/a             n/a
      buff               5           n/a             n/a
      fdc                1           n/a             n/a
      inv                1           n/a             n/a
      nor2               2           n/a             n/a
      or2                1           n/a             n/a
      xgnd               1           n/a             n/a
------------------------------------------------------------
Total     7             12           n/a         n/a


 

This particular part of the tutorial is a bit confusing intially but please try to correlate the timing report and the constraints report with the schematic drawn.  It will make it much more easier to understand the process.

It should be evident that the input timing constraints cannot be haphazardly provided as they play a crucial role in correct functioning of the circuit.  Also, depending on the output constraints, the synthesizer may tend to generate a netlist accordingly.  So providing constraints is a very crucial decision that can affect the entire synthesis process.

Though i have provided a very simple example, it is meant to understand the flow of design and to show some of the intricacies involved.  I changed the output timing constraints by providing a window.  Notice that i didn't go beyond 7 ns but just allowed the synthesis to have a tolerance in the output timing constraint.  One can as well try various other options for constraints and synthesis to try and meet a specific goal.

Created by Tarak: March 1998.