This tutorial is meant to provide a quick-start to generating schematics of the synthesized designs.  The design under consideration was a simple one, and in case of modular designs, one can play around with the information presented here and sort out the details.  I will try to run a modular design and update this page as I uncover new information.  ANY NEW INFORMATION THAT YOU UNCOVER IS IMPORTANT TO US AND SO PLEASE FEEL FREE TO EMAIL THEM TO US SO THAT WE CAN POST IT FOR THE WHOLE CLASS TO ACCESS.

There are different steps to generating the schematic (e.g. from the synthesizer itself), however to provide a continuity to the previous four parts of this tutorial, we will use a stand-alone approach to schematic generation.

Click on the hammer-icon (second row, first column; next to the synthesizer thunder-bolt iconized button).  The following form will appear:
 
 

Click on the Schematic tab (located on the top of the sub-window).  The sub-window will modify to display as shown below:
 
 

Select the options as shown in the figure above and hit apply.

Now hit "generate schematic" button.  This will kick-off a process in the Synergy command sub-window and open up a "process progress" window.  After everything's done, the Synergy command sub-window will have the following list of messages:
 
 

That means that the schematic generation is done.  Feel free to view the schematic generation log file located in the run directory (file name = synschgen.log).

To view the logic structure (and the signal names) of the netlist, which is now converted to a schematic, open a console/terminal and change the pwd to the run directory.  In the run-directory, type concept and hit enter.  This will start-off concept and if the the schematic was generated correctly, the following window will appear.  Concept is another tool in the Cadence set of tools.
 
   

To view the logic, click on the "push" button and select logic.  Then go to the black-subwindow and click on the blue-box.  This will push the heirarchy to reveal the logic beneath.  This logic will consist of XC4000E_SYN library components and all the signal names used by the synthesizer will be visible.  For simple designs, this will be very useful in identifying timing paths.

Right now, for the present assignment, this much information should be more than adequate.  Please look up the Synergy tutorials listing for more additions.

PLEASE FEEL FREE TO TRY OUT VARIOUS OPTIONS/TOOLS AND EXPLORE!!!