OBJECTIVE: The aim of this tutorial is to help get a quick-start on synthesizing a behavioral design using Synplify, create a simulation model and a bit-file for FPGA download.
                It will is not meant as an indepth tutorial for the tools involved for the above-mentioned process.

DIRECTORY STRUCTURE:  The initial directory structure looked like:
 

Figure 1

The behavioral model used for this example is combi.vhd.  This vhdl source file is located in the vhdl directory (figure 1).  I used the vhdl directory for vhdl simulation/synthesis and the cadence directory for p&r/simulation model generation and other processes related to cadence implementation.

Figure 2

Step2: Click on the CHANGE button below the Target field.  A pop-up window will appear (figure 3).  Select the appropriate FPGA and the associated options (In our case, the FPGA manufacturer is XILINX, the series is XC4000E and the particular chip is XC4005E with a PC84 package).  Note that the result file field will show a file name with an extension .xnf for the Xilinx target option, once the appropriate target has been selected.  It is wise to force GSR usage (global set/reset usage) for the purpose of creating a simulation model.  IF YOUR DESIGN IS A BLACK-BOX THAT WILL BE INSTANTIATED AS A COMPONENT IN THE FINAL VHDL DESIGN, DISABLE I/O INSERTION.  This will disable Synplify from inserting i/o pads and will create a library component (*.xnf file) which can be used in the final design.  IF THIS DESIGN IS NOT A BLACK-BOX DESIGN, ENABLE THE I/O INSERTION FOR PAD PLACEMENT.
 

Figure 3

Step3: Hit the large RUN button.

Watch as the large letter in red shows the various stages of synthesis.  In case or errors or warnings, the appropriate messages will appear in the small scrolling window shown in Figure 2.

If there are errors or warnings, double-click on the errors/warnings and observe the messages and make appropriate changes.  If there are no errors/warnings, the synthesis is done.

To view the RTL (structural) view of the synthesis, pull down the HDL ANALYST menu option from the menu-bar and select the RTL_VIEW.  This will show the structural synthesis.  In the example provided, Synplify will synthesize two modules (as the original VHDL code has two modules) as shown in figure 4 below.  To view below the modules, push down the hierarchy.  It is just possible that the design may be very large and in such a case, Synplify will generate a few pages of RTL views.  Peruse through the sheets to view the schematics (the three arrow-icons shown on the right side of the buttons-toolbar are associated with push/pop heirarchy and sheet-viewing).

Not shown in this tutorial, but if you wish to view the final layout on the FPGA, select the TECHNOLOGY VIEW from the HDL-ANALYST pull-down menu option on the menu-bar.
 

Figure 4

PLEASE CLICK ON THIS LINK TO VIEW IMPORTANT INFORMATION ON CONSTRAINTS AND SOME SYNTHESIS OPTION.

        At this stage, you can have appropriate xnf files generated by any tool either on PC or UNIX.  It isn't essential that you should have used Synplify as in Step 1 (above this stage).  However, for simulation model generation, it is ADVISABLE that your synthesized design has used GSR signal.  I have tried a couple of times without using the GSR signal and Cadence simulation model generation didn't like it very much.  I don't remember if i had troubles with P&R when i didn't use GSR, but to the best of my knowledge and recollection, this shouldn't matter if you intend to simply generate a final bit-file for downloading it to the FPGA rather than generating a simulation model.  And more i try to recollect i am pretty sure i was able to do P&R and generate a bit-file without having to use the GSR.

Figure 5

Figure 6

Figure 7

For the design option, enter the name of the xnf file generated by Synplify (in our case, combi).

Click on time_units button located on the left-side of the window in figure 7 and enter "100ps" (without the quotes).  This sets the minimum simulation time to 100ps (the lowest possible).

Click on the compiler button located on the left side of the window shown in figure 7.  The window shown in figure 8 (below) will pop-up.
 

Figure 8

In the compile type field, delete "logic" and enter "backplane" (without the quotes).  Hit apply and then quit.

From the window shown in figure 7, click "global" button located on the left side of the window.  The window shown in figure 9 (below) should pop-up.

In the root drawing field of the window in figure 9, enter the name of the xnf file generated by Synplify (without the extension; in our case, combi).  DO NOT QUIT THIS WINDOW, YET!!
 

Figure 9

Click on the library side-button in the window of figure 9 and "add" the following libraries in the window that pops up (figure 10).  (These libraries aren't actually needed for place/route and generating a bit-stream but are needed in case one wants to add xilinx components to the black-box schematic generated by Cadence Concept).  Hit done when done.
 

Figure 10

Now click on the USE side-button of the window in figure 9 and enter the following work directory (this directory is used by Concept Schematic tool).  Hit done.
 

Figure 11

Now in the window of figure 9, hit apply (VERY IMPORTANT) and then quit.

At this stage, the window in figure 7 should be open.  Hit exit button located to the left of the window in figure 7.

Now from the window in figure 6, click on the ASIC/PIC DESIGN button and select Xilinx design.  The window in figure 6 should now appear as shown below in figure 12.
 

Figure 12

Wait a few seconds till you see the messages shown in the message sub-window of the window in figure 12.  Click on SETUP.

The window shown in figure 13 (below) should appear.
 

Figure 13

In this case, we want to import the xnf file generated by Synplify and then modify the constraints file for pad-locations (hence we must have a constraints file template) and then do place-route of the xnf file.  Notice the *.xnf because we might have many xnf files (black-boxes xnfs and the outer-shell xnf, generated by Synplify) to import to create a complete design.

So, enter the fields as shown in figure 14 below.  It is very important to de-select "generate netlist" option.  Also, provide the correct path for importing the xnf file.

Once done, hit done and the window in figure 14 will close.
 

Figure 14

Now in the window shown in figure 12, click on the netlist button.  Now the tool will try to import the specified xnf file.  If successful, the message-subwindow in the window shown in figure 12 will show that the netlist import step was successful.

Now we want to place/route our design and generate the bit file.  Prior to this, we must modify the pad locations.  So go to the Xilinx.run directory (created by Cadence) in the cadence directory (present directory) and open the constraints file (*.cst).  For pad-placement constraints, scroll to the end of the text file (as shown in figure 15 below).
 

Figure 15

I wanted my pads to be located on the following pins and so i modified the constraints file (figure 15) as shown in figure 16 below).
 

Figure 16

Now from the window shown in figure 12, click on P&R iconized button.  It will take a considerable time to do P&R and so please be patient.  Wait till the message sub-window of the window in figure 12 shows that the step was successful.  It will beep when it is done.  In case of errors, it will tell that there were errors.  In case of errors, refer to the appropriate files indicated in the message sub-window and try to identify and correct errors.

After successfully doing P&R, the bit-stream will be located in the xilinx.run directory located in the cadence directory.  If the simulation model is not needed, then the bit-stream can be down-loaded on the FPGA and be tested out using xchecker.

To generate a simulation model, keep on reading and performing the tasks.

After successfully doing P&R, click on the SimModel iconized button of the window in figure 12.  It will take considerable time to generate the simulation model and so please be patient.  Wait till the message sub-window of the window in figure 12 shows that the step was successful.  It will beep when it is done.  In case of errors, it will tell that there were errors.  In case of errors, refer to the appropriate files indicated in the message sub-window and try to identify and correct errors.

After successfully completing the above step, click on the Physical iconized button in the window of figure 12.  It will take considerable time to back-annotate and so please be patient.  Wait till the message sub-window of the window in figure 12 shows that the step was successful.  It will beep when it is done.  In case of errors, it will tell that there were errors.  In case of errors, refer to the appropriate files indicated in the message sub-window and try to identify and correct errors.

Once this is done, click on the Digital Sim button (located towards the bottom) of the window in figure 12.  The window should now change to appear as shown in figure 6.

Now from the window in figure 6, click on the SimControl iconized button.  The window shown in figure 17 should now appear.

Click on the Load button (located to the left of the window in figure 17, below) and choose "load design".  Notice the green READY located on the upper left side of the window in figure 17.  When this changes to a BUSY in red, it is busy and refrain from doing anything while it is BUSY.
 

Figure 17

 

Now in the window of figure 6, click on the wave-view button.  The window shown in figure 18 (below) should appear.  It will not have the signals and waveforms shown in the window below and so do not worry!!!
 

Figure 18

Now in the window of figure 17, click on START/STOP and select "START SIM".  This will prepare wave-bench for simulation of the design.

After it is done, at the scl> prompt of the command sub-window of the window in figure 17, "open" the ports for simulation waveview by typing
 
               open "<sig_name>";
 
where <sig_name> is the name of the port to be viewed in the wave-view-window of figure 18.  DO NOT FORGET THE QUOTES THIS TIME!!!  AND THE SEMI-COLON AT THE END IS VERY IMPORTANT!  It sort of "terminates" or ends the present command.

Once all the ports have been "opened", the signals shown in figure 18 should appear.

We will now define our clock by typing the following command at the scl> command prompt in the command sub-window of figure 17.
                assert "clk", 1(100,2);

where clk is the signal being asserted, 100 is the time-period and 2 tells wave-tool that there are two periods in 100ns (effectively, a clock with 50% duty cycle and a time-period of 100ns).  Do not forget the quotes and the semi-colon.

To force a particular signal high or low, we can enter the following command:
            force "<sig_name>",1;
            force "<sig_name>",0;
where the first command forces the <sig_name> to a '1' and the second command forces the <sig_name> to a '0'.

To simulate for a particular duration of time, we can enter the following command:
           sim 117ns;
which will simulate the design for 117 ns from the present simulation time.

For more help on this simulation tool and commands please refer to OpenBook.  IT IS ALSO POSSIBLE TO WRITE A SCRIPT FILE TO PERFORM A BATCH SIMULATION RATHER THAN HAVING TO ENTER THE COMMANDS ON THE COMMAND LINE.

For immediate help, click on the help button of the window in figure 17.

There are lots of options and features and capabilities but for now, this should be more than enough to get an initial grasp on RAPID PROTOTYPING.

Created by Tarak: April, 1998