EE497i Tutorials

Take this link to view the Leapfrog VHDL Compilation and Simulation Quick-Start tutorial

Take this link to view the VHDL Synthesis (and simulation) Quick-Start tutorial

RAPID PROTOTYPING AND FPGAs

• Introduction to Rapid Prototyping - PowerPoint presentation introducing rapid system prototyping concepts in general and the EE497I class topics in specific.
• Programmable Logic and Application Specific Integrated Circuits - WARNING -- 284K .pdf File... This link provides background material about the digital hardware implementation technologies and options available for rapid system prototyping. This is a draft of my chapter from the 1996 Active Electronic Component Handbook. Most of the material had been reproduced faithfully in this conversion, but some figures are missing. Refer to the McGraw Hill publication (ISBN 0-07-026692-1) for the full text, figures, and many other chapters of useful electronics reference material.
• Mega-Functions and Intellectual Property -- follow this link to the Altera, Actel, and EDA Today slides on IP and Cores.
• Xilinx Technology-Specific Reading Assignment: an overview of specific details of the Xilinx families of FPGAs and their relevant architectural features are contained in their 3-day University seminar slides (see links below). Full and up-to-date details are contained in the Xilinx Databook -- study the XC4000 Product Family chapter of the "databook.pdf" file, or go on-line to the Xilinx Website for the XC4000E FPGA Family DataSheet.  Also, don't forget to look up the differences between the various XC4000 family parts (4000, 4000a, 4000E, 4000XL, 4000XV). Specific and up-to-date information about the entire Xilinx product line is available here. When you study the RASSP Testability Module (43), it will also be a good idea to review the IEEE1149.1 (JTAG) features and capabilities of the Xilinx 4000 family standard parts.

Xilinx University Seminar Day 1 -- Xilinx University Seminar Day 2 -- Xilinx University Seminar Day 3

CAD TOOLS (Cadence, Synplicity, Xilinx, ...)

• XILINX M1 TOOLS Quick-Start Tutorial instructions to guide you through the Xilinx tools and the DEMO board download procedures.
• VHDL and Leapfrog Tutorials: The following tutorials should be helpful in using Leapfrog for the first time.
• Leapfrog Quickstart guide for compiling:  (Warning: Lots of graphics!) Part - I:  Compiling the code and Part - II: Simulation
• Sample Codes for use with the guide: Sample VHDL behavioral model for testing the Leapfrog simulator, Sample VHDL test bench for testing the above model, and its figure1 for clarity.
• Synergy Tutorial (NOTE: This is Legacy Information from Spring Semester 1998 -- we will now be using the Synplicity VHDL Synthesis tool for the Fall `98 class):
• VHDL Code used for the tutorial
• Part-I of the tutorial
• Part - II of the tutorial
• Part - III of the tutorial
• Part - IV of the tutorial
• Part - V of the tutorial (Schematic Generation)

Note: The reason that the tutorial is split into four parts is to avoid loading all the gif images onto a single page.

VHDL MODELING AND SYNTHESIS

• EE497I VHDL Reference and Tutorial Information -- this is a link to all EE497I class-specific VHDL reference information and materials, as well as to RASSP program instructional materials (VHDL Introduction, Structural - Behavioral - System Level Modeling, and Synthesis).
• BASIC VHDL (RASSP E&F Module 10) -- Presentation material used used for 9/22 and 9/24 class lectures.  Use THIS LINK for a frames version of Module 10 (best suited for 1024X768 resolution or better)
• BEHAVIORAL VHDL (RASSP E&F Module 12) -- Presentation material for the 9/29 lecture.  Again, there is a frames version of Module 12 as well.
• A sample VHDL program which shows a possible way to ignore timing and synchronization details at a very abstract behavioral description.
• A sample test bench this is left over from Spring`98 homework #2 .  You can also create your own test-bench to test your model.  Please read the comments mentioned in the test-bench file if you plan to use this test-bench.

  Here is a link to my draft exam review document - Friday 10/16

RASSP PROGRAM (OTHER) TUTORIALS

• RASSP Methodology Overview -- The EE497I class will be using a number of RASSP modules (mostly VHDL reference related). Consequently, you should review this RASSP methodology module to understand the program, it's objectives, and it's results. Pay particular attention to the hardware prototyping sections; they are the most relevant to our class.
• Testability and Design for Test -- RASSP Module 43 -- reading assignment for lectures on 11/17 - ...

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Last Meddled With: 10/15/04 - D. Landis