Xilinx University Program Internet Seminar Day 2 - July,17 1997
Agenda - Day 2
XC9500 CPLDs
XC9500 Function Block
XC9500 Product Family
XC4000 Architecture
XC4000 Configurable Logic Blocks
Look Up Tables
XC4000E I/O Block Diagram
Xilinx FPGA Routing
Other FPGA Resources
What’s Really In that Chip?
XC4000E Fastest 5 V FPGA Family
Cost Reduction & Density Increases
Process Technology and Supply Voltage
XC4000XL 3.3 V, 0.35m, 5 Volt Compatible
XACTstepTM M1 Software
Foundation Overview
Foundation Project Manager
Schematic Entry
ABEL and VHDL Text Entry
Simulation
Libraries, Macros & Attributes
Implementation - M1 Design Manager
Flow Engine
Easy Control of Implementation Options
XACT-M1 Design Flow
M1 Design Flow Programs
Xilinx Student Edition from Prentice Hall Publishers
Xilinx Student Edition Development Boards
Home Page: http://www.cedcc.psu.edu/
Other information: used in PSU -- EE497I Class Rapid System Prototyping