Xilinx University Program Internet Seminar Day 3 - July,18 1997
Agenda - Day 3
FPGAs Provide Outstanding DSP Performance
FIR FILTER EXAMPLE
Traditional FIR Filter Implementation
Distributed Arithmetic (DA) Filter Design
Resource Tradeoffs for Higher Performance
XC4085XL 10 Times Faster Than TMS320C6x
FPGA DSP is Lower Cost
Where FPGA-Based DSP is Used
How Reconfiguration Helps DSP
Reconfigurable Logic - Research vs. Component $
XC6200 Reconfigurable Processing Unit
Dynamic & Partial Reconfiguration
XC6200 Architecture
The Real Cost of Ownership
Cost Calculations - Basic Model
Cost Calculations - Market Model
Hardwire Technology Model
Course Recommendations
Computer Lab Requirements
Typical Lab Setup
CPLD or FPGA?
Xilinx Donation Policy
Hardware Boards
Why Xilinx?
Home Page: http://www.cedcc.psu.edu/
Other information: used in PSU -- EE497I Class Rapid System Prototyping