Specifications.

**Sense Amplifier**

Floorplan

Pinout

Simulations

Timing analysis

Power analysis

Comments

Block Diagram of the entire SRAM chip.

One KByte Static RAM chip using 6T SRAM cell. Organized as 128 * 8 * 8 SRAM cells Data Write Time: 20 ns. Data Read Time: 13 ns. Average Power consumption: 17.25 mW  Approximate Transistor count: 51,000 Chip Size: without pads :  668.98 * 1275.74 Chip size : with pads      : 2580 * 2580  (in micron^2) Total Pins used: 25 Pin name Function A9 – A0 Address lines DB7 - DB0 Bi-directional Data bus CE  (Active low) Chip Enable WE (Active low) Write Enable OE  (Active low) Output Enable Vdd, Gnd Power rails. (2 each) .

Chip function: The One KByte SRAM chip is capable of storing and retrieving data. The capacity of the chip is One KByte (8092 bits). The chip uses a total of 25 pins on the pad frame and is made up of approximately 51,000 transistors. 

The above diagram shows the structure of the SRAM. We will be using a Six transistor SRAM cell to store every bit. The total number of address lines needed for accessing the 1024 locations is ten. I have organized the SRAM into a 128 * 8 * 8 structure so as to make the final layout size more symmetrical. The total layout area permitted is 1800 * 1800 and so it makes sense to have a square layout instead of a rectangular layout.

The entire chip has been built using MAX layout editor and the system is fully functional. We have simulated the worst case condition for the SRAM and the waveforms are as shown in the simulation section. 

We have done a lot of research on the functioning of the circuit with and without the sense amplifier. You can get a comprehensive report of the sense amplifier by clicking on the "Sense Amplifier" link alongside.  

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